Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N

[Usha P (Code Review)]

Attention is currently required from: Anilkumar N, Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla.
Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59937 )

Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
......................................................................

Patch Set 6:

(1 comment)

File src/mainboard/intel/adlrvp/gpio_n.c:

https://review.coreboot.org/c/coreboot/+/59937/comment/996f1745_c484c916 
PS5, Line 52: /*TCP1_DISP_AUX_P_BIAS_GPIO*/
            : 	PAD_CFG_GPO(GPP_E20, 1, PLTRST),
            : 	/*TCP1_DISP_AUX_N_BIAS_GPIO*/
            : 	PAD_CFG_GPO(GPP_E21, 0, PLTRST),
            : 	/*TCP0_DISP_AUX_P_BIAS_GPIO*/
            : 	PAD_CFG_GPO(GPP_E22, 0, PLTRST),
            : 	/*TCP0_DISP_AUX_N_BIAS_GPIO*/
            : 	PAD_CFG_GPO(GPP_E23, 1, PLTRST),
> I am guessing here from the pad names, but should these be NF6 for AUX BIAS functionality?

These are GPIO pins used for providing BIAS functionality to the AUX lines. We will configure them based on the orientation of the display device plugged on Type-C.