Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63656 )
Change subject: mb/msi/ms7d25: Configure PCIe Root Ports ......................................................................
mb/msi/ms7d25: Configure PCIe Root Ports
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f --- M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7d25/romstage_fsp_params.c 2 files changed, 206 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/63656/1
diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 21e7625..b46bbab 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -79,8 +79,46 @@ [DDI_PORT_4] = DDI_ENABLE_HPD, }"
+ register "hybrid_storage_mode" = "1" + + register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[3]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[4]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[5]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[7]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[8]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[9]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[10]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[11]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[12]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[13]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[14]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[16]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[17]" = "PCIE_CLK_FREE_RUNNING" + device domain 0 on + device ref pcie5_0 on + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + .PcieRpL1Substates = L1_SS_DISABLED, + .pcie_rp_aspm = ASPM_DISABLE, + }" + smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong" + "PCI_E1" "SlotDataBusWidth16X" + end device ref igpu on end + device ref pcie4_0 on + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + .PcieRpL1Substates = L1_SS_DISABLED, + .pcie_rp_aspm = ASPM_DISABLE, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M2_1" "SlotDataBusWidth4X" + end device ref crashlog off end device ref xhci on end device ref cnvi_wifi on end @@ -91,6 +129,171 @@ device ref heci3 off end device ref heci4 off end device ref sata on end + + device ref pcie_rp1 on + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" + "PCI_E2" "SlotDataBusWidth1X" + end + device ref pcie_rp2 on + register "pch_pcie_rp[PCH_RP(2)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" + "PCI_E4" "SlotDataBusWidth1X" + end + device ref pcie_rp3 on + # i225 Ethernet + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp4 off end + + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" + "PCI_E3" "SlotDataBusWidth4X" + end + device ref pcie_rp6 on + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp8 on + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M2_3" "SlotDataBusWidth4X" + end + device ref pcie_rp10 on + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp11 on + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp12 on + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + + # These are not enabled. The Flex I/O mode is SATA to cover all 8 SATA ports. + # There is an ASMedia switch on-baord to mux the SATA ports 7, 8 and PCIe + # 9-12, 21-24 to M2_3 and M2_4 slots + device ref pcie_rp13 off end + device ref pcie_rp14 off end + device ref pcie_rp15 off end + device ref pcie_rp16 off end + device ref pcie_rp17 off end + device ref pcie_rp18 off end + device ref pcie_rp19 off end + device ref pcie_rp20 off end + + device ref pcie_rp21 on + register "pch_pcie_rp[PCH_RP(21)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M2_4" "SlotDataBusWidth4X" + end + device ref pcie_rp22 on + register "pch_pcie_rp[PCH_RP(22)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp23 on + register "pch_pcie_rp[PCH_RP(23)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp24 on + register "pch_pcie_rp[PCH_RP(24)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + + device ref pcie_rp25 on + register "pch_pcie_rp[PCH_RP(25)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M2_2" "SlotDataBusWidth4X" + end + device ref pcie_rp26 on + register "pch_pcie_rp[PCH_RP(26)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp27 on + register "pch_pcie_rp[PCH_RP(27)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp28 on + register "pch_pcie_rp[PCH_RP(28)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref p2sb on end device ref hda on end device ref smbus on end diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index e6b8515..c45950f 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -51,6 +51,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { memupd->FspmConfig.FirstDimmBitMask = 0xA; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0;
memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); }
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Michał Żygowski (Code Review)