Change in coreboot[master]: soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63233 )

Change subject: soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type
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soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type

Contradicting the PPR #57243 version 1.56, the I2C3 pad control register
in the MISC ACPIMMIO region is the same new I23C pad type as the
corresponding registers for I2C0..2 and not the older I2C pad control
register type used on Picasso and Cezanne. All I2C pads being of the new
I23C type is in line with the GPIOMUX settings for the pins used by
I2C0..3 that can alternatively connect the pins to an I3C controller.

Signed-off-by: Felix Held 
Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63233
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Fred Reitberger 
Reviewed-by: Raul Rangel 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/sabrina/Kconfig
M src/soc/amd/sabrina/i2c.c
2 files changed, 1 insertion(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved
  Fred Reitberger: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 66719a6..6924ce4 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -53,7 +53,6 @@
    select SOC_AMD_COMMON_BLOCK_GRAPHICS	# TODO: Check if this is still correct
    select SOC_AMD_COMMON_BLOCK_HAS_ESPI	# TODO: Check if this is still correct
    select SOC_AMD_COMMON_BLOCK_I2C
-	select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL
    select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL
    select SOC_AMD_COMMON_BLOCK_IOMMU
    select SOC_AMD_COMMON_BLOCK_LPC		# TODO: Check if this is still correct
diff --git a/src/soc/amd/sabrina/i2c.c b/src/soc/amd/sabrina/i2c.c
index 1008f56..e805eff 100644
--- a/src/soc/amd/sabrina/i2c.c
+++ b/src/soc/amd/sabrina/i2c.c
@@ -39,12 +39,7 @@
    if (bus >= ARRAY_SIZE(config->i2c_pad))
    	return;

-	/* The I/O pads of I2C0..2 are the new I23C pads and the I/O pads of I2C3 still are the
-	   same I2C pads as in Picasso and Cezanne. */
-	if (bus <= 2)
-		fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
-	else
-		fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
+	fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
 }

const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)