[S] Change in coreboot[master]: soc/intel/common: Fix long delay when ME is disabled

[Subrata Banik (Code Review)]

Attention is currently required from: Sean Rhodes, Tarun Tuli, Paul Menzel, Sridhar Siricilla, Angel Pons.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74435 )

Change subject: soc/intel/common: Fix long delay when ME is disabled
......................................................................

Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/74435/comment/42c5327d_eac29903 
PS1, Line 14: 
            : This is because the current code only checks if the ME is
            : disabled for CSE LITE SKUs. With this patch, boot times are
            : approximately 5 seconds quicker:
> "the idea"?

I mean to say the implementation is to make  CSE function disable using PMC IPC

below two lines are justifying the same here. 
```
[INFO ]  CSE is disabled, continuing boot
[INFO ]  Disabling Heci using PMC IPC
```

this is expected behavior