[M] Change in coreboot[main]: soc/intel/lockdown: Allow locking down SPI and LPC in SMM

[Michał Kopeć (Code Review)]

Attention is currently required from: Christian Walter, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Jeff Daly, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Paul Menzel, Pranava Y N, Subrata Banik, Tarun, Tim Chu, Vanessa Eusebio, Werner Zeh.

Michał Kopeć has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/85278?usp=email )

Change subject: soc/intel/lockdown: Allow locking down SPI and LPC in SMM
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Patch Set 3: Code-Review+1

(1 comment)

File src/soc/intel/alderlake/finalize.c:

https://review.coreboot.org/c/coreboot/+/85278/comment/e19caa76_c8d3a8db?usp... :
PS3, Line 88: 	if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
> Excuse my ignorance, why is `acpi_is_wakeup_s3()` added?

As I understand it, it's because the payload is not executed in the S3 resume path, so it won't have the chance to call APM_CNT_FINALIZE itself.

src/southbridge/intel/lynxpoint for example handles it the same way.