Change in coreboot[master]: mb/google/volteer: Add error handling

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45176 )

Change subject: mb/google/volteer: Add error handling
......................................................................

mb/google/volteer: Add error handling

Coverity detects missing error handling after calling function
tlcl_lib_init. This change checks the function tlcl_lib_init return
value and handles error properly.

Found-by: Coverity CID 1432491
TEST=None

Signed-off-by: John Zhao 
Change-Id: Ife38b1450451cb25e5479760d640375db153e499
---
M src/mainboard/google/volteer/mainboard.c
1 file changed, 8 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/45176/1

diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index 849869a..23c3e92 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -12,6 +12,7 @@
 #include <soc/ramstage.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <variant/gpio.h>
+#include <vb2_api.h>

static void mainboard_init(struct device *dev)
 {
@@ -43,7 +44,13 @@

void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg)
 {
-	tlcl_lib_init();
+	int ret;
+	ret = tlcl_lib_init();
+	if (ret != VB2_SUCCESS) {
+		printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
+		return;
+	}
+
    if (cr50_is_long_interrupt_pulse_enabled()) {
    	printk(BIOS_INFO, "Enabling S0i3.4\n");
    } else {

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45176 )

Change subject: mb/google/volteer: Add error handling
......................................................................

Patch Set 1: Code-Review+2

[Caveh Jalali (Code Review)]

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45176 )

Change subject: mb/google/volteer: Add error handling
......................................................................

Patch Set 1: Code-Review+1

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45176 )

Change subject: mb/google/volteer: Add error handling
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45176 )

Change subject: mb/google/volteer: Add error handling
......................................................................

mb/google/volteer: Add error handling

Coverity detects missing error handling after calling function
tlcl_lib_init. This change checks the function tlcl_lib_init return
value and handles error properly.

Found-by: Coverity CID 1432491
TEST=None

Signed-off-by: John Zhao 
Change-Id: Ife38b1450451cb25e5479760d640375db153e499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Caveh Jalali 
Reviewed-by: Angel Pons 
---
M src/mainboard/google/volteer/mainboard.c
1 file changed, 8 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Caveh Jalali: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index 849869a..23c3e92 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -12,6 +12,7 @@
 #include <soc/ramstage.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <variant/gpio.h>
+#include <vb2_api.h>

static void mainboard_init(struct device *dev)
 {
@@ -43,7 +44,13 @@

void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg)
 {
-	tlcl_lib_init();
+	int ret;
+	ret = tlcl_lib_init();
+	if (ret != VB2_SUCCESS) {
+		printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
+		return;
+	}
+
    if (cr50_is_long_interrupt_pulse_enabled()) {
    	printk(BIOS_INFO, "Enabling S0i3.4\n");
    } else {

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45176 )

Change subject: mb/google/volteer: Add error handling
......................................................................

Patch Set 2:

Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9
"QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19076
"QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19075
"QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/19074
"QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19073
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/19072
"HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19080
"HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19079
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19078
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19077

Please note: This test is under development and might not be accurate at all!