Change in coreboot[master]: soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100

[Felix Held (Code Review)]

Attention is currently required from: Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59933 )

Change subject: soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100
......................................................................

soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100

Use a read modify write sequence when setting the SPI_USE_SPI100 bit in
the SPI100_ENABLE register. This avoids clearing other bits in the
register which might cause instabilities of the SPI interface. The
reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and
doesn't zero out the other bits.

TEST=None

Signed-off-by: Felix Held 
Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790
---
M src/soc/amd/stoneyridge/southbridge.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/59933/1

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index de27ac5..63bfd83 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -242,7 +242,7 @@
    			(fast << SPI_FAST_SPEED_NEW_SH) |
    			(alt << SPI_ALT_SPEED_NEW_SH) |
    			(tpm << SPI_TPM_SPEED_NEW_SH));
-	spi_write16(SPI100_ENABLE, SPI_USE_SPI100);
+	spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE));
 }

static void sb_disable_4dw_burst(void)