Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning

[Felix Held (Code Review)]

Attention is currently required from: Bao Zheng, Jason Glenesk, Nico Huber, Raul Rangel, Marshall Dawson, Paul Menzel, Zheng Bao, Rob Barnes.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 )

Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
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Patch Set 7:

(1 comment)

File src/soc/amd/cezanne/chip.h:

https://review.coreboot.org/c/coreboot/+/59918/comment/b1e0ff8f_1ba07110 
PS7, Line 112: 	uint8_t edp_physel;
> > It is a upd value which is sent to FSP. We need to give it a clear size. […]

i'd also strongly prefer to use an enum here; same for the corresponding code in picasso. something like this untested code below should work and the value can just be assigned to the mcfg->edp_physel upd struct member in fsp_m_params.c like it is done now, since it still fits in the uint8_t of mcfg->edp_physel:

enum {
    EDP_TUNE_SEL_DP0 = (1 << 0),
    EDP_TUNE_SEL_DP1 = (1 << 1),
    EDP_TUNE_SEL_DP2 = (1 << 2),
    EDP_TUNE_SEL_DP3 = (1 << 3),
} edp_physel;

in the devicetree setting you'll need something like
register "edp_physel" = "EDP_TUNE_SEL_DP0"

i'm ok with doing this change or picasso and cezanne as a follow-up