Change in ...coreboot[master]: vendorcode/amd/agesa/{f12,f14,f15tn,f16kb} PcieConfigLib.c: Remove lo...

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33362

Change subject: vendorcode/amd/agesa/{f12,f14,f15tn,f16kb} PcieConfigLib.c: Remove logical 'or' of equal expressions
......................................................................

vendorcode/amd/agesa/{f12,f14,f15tn,f16kb} PcieConfigLib.c: Remove logical 'or' of equal expressions

Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41
Signed-off-by: Elyes HAOUAS 
---
M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
4 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33362/1

diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index ee7ef01..fd67858 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -202,7 +202,7 @@
   IN      PCIe_ENGINE_CONFIG   *Engine
   )
 {
-  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
     return 0;
   }
   if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 788c0b7..3c0f949 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -178,7 +178,7 @@
   IN      PCIe_ENGINE_CONFIG   *Engine
   )
 {
-  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
     return 0;
   }
   if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 6466862..bf06160 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -205,7 +205,7 @@
   IN      PCIe_ENGINE_CONFIG             *Engine
   )
 {
-  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
     return 0;
   }
   if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 8e5e3dd..91a4be5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -205,7 +205,7 @@
   IN      PCIe_ENGINE_CONFIG             *Engine
   )
 {
-  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
     return 0;
   }
   if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {

Change in ...coreboot[master]: vendorcode/amd/agesa/{f12,f14,f15tn,f16kb} PcieConfigLib.c: Fix logic...

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/33362 )

Change subject: vendorcode/amd/agesa/{f12,f14,f15tn,f16kb} PcieConfigLib.c: Fix logical 'or' of equal expressions
......................................................................

vendorcode/amd/agesa/{f12,f14,f15tn,f16kb} PcieConfigLib.c: Fix logical 'or' of equal expressions

Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41
Signed-off-by: Elyes HAOUAS 
---
M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
4 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33362/2

Change in ...coreboot[master]: vendorcode/amd/agesa/{f12,f14,f15tn,f16kb} PcieConfigLib.c: Fix logic...

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33362 )

Change subject: vendorcode/amd/agesa/{f12,f14,f15tn,f16kb} PcieConfigLib.c: Fix logical 'or' of equal expressions
......................................................................

Patch Set 2: Code-Review-1

(1 comment)

https://review.coreboot.org/#/c/33362/2/src/vendorcode/amd/agesa/f12/Proc/GN... 
File src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c:

https://review.coreboot.org/#/c/33362/2/src/vendorcode/amd/agesa/f12/Proc/GN... 
PS2, Line 205: 
The second test here should be for Engine->EngineData.EndLane

Change in ...coreboot[master]: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix logical 'or' ...

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33362

to look at the new patch set (#3).

Change subject: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix logical 'or' of equal expressions
......................................................................

vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix logical 'or' of equal expressions

Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41
Signed-off-by: Elyes HAOUAS 
---
M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
4 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33362/3

Change in ...coreboot[master]: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix logical 'or' ...

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33362 )

Change subject: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix logical 'or' of equal expressions
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/#/c/33362/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/33362/3//COMMIT_MSG@7 
PS3, Line 7: Fix logical 'or' of equal expressions
Please update after the correct fix. Maybe something like:
> Fix check for valid phy lanes

https://review.coreboot.org/#/c/33362/3//COMMIT_MSG@8 
PS3, Line 8: 
Please add:
> Found-by: GCC with flag …

Change in ...coreboot[master]: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix check for val...

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33362

to look at the new patch set (#5).

Change subject: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix check for valid PhyLane
......................................................................

vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix check for valid PhyLane

Found using GCC with flag -Wlogical-op

Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41
Signed-off-by: Elyes HAOUAS 
---
M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
4 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33362/5

Change in ...coreboot[master]: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix check for val...

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33362 )

Change subject: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix check for valid PhyLane
......................................................................

Patch Set 5: Code-Review+2

Change in ...coreboot[master]: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix check for val...

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33362 )

Change subject: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix check for valid PhyLane
......................................................................

Patch Set 5: Code-Review+1

Change in ...coreboot[master]: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix check for val...

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33362 )

Change subject: vendorcode/agesa/{f12,f14,f15tn,f16kb}/GNB/Modules: Fix check for valid PhyLane
......................................................................

Patch Set 5:

(1 comment)

Please fix the commit summary (usual limit is 55 chars,
72 should be the absolute maximum).

https://review.coreboot.org/#/c/33362/5//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/33362/5//COMMIT_MSG@7 
PS5, Line 7: vendorcode/agesa
`vendorcode/agesa:` would be enough for the prefix, I guess

Change in ...coreboot[master]: vendorcode/agesa: Fix check for valid PhyLane

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Angel Pons, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33362

to look at the new patch set (#6).

Change subject: vendorcode/agesa: Fix check for valid PhyLane
......................................................................

vendorcode/agesa: Fix check for valid PhyLane

Found using GCC with flag -Wlogical-op

Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41
Signed-off-by: Elyes HAOUAS 
---
M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
4 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33362/6

Change in ...coreboot[master]: vendorcode/agesa: Fix check for valid PhyLane

[Nico Huber (Code Review)]

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33362 )

Change subject: vendorcode/agesa: Fix check for valid PhyLane
......................................................................

vendorcode/agesa: Fix check for valid PhyLane

Found using GCC with flag -Wlogical-op

Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33362
Reviewed-by: Kyösti Mälkki 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
4 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index ee7ef01..c76b290 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -202,7 +202,7 @@
   IN      PCIe_ENGINE_CONFIG   *Engine
   )
 {
-  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) {
     return 0;
   }
   if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 788c0b7..dae9899 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -178,7 +178,7 @@
   IN      PCIe_ENGINE_CONFIG   *Engine
   )
 {
-  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) {
     return 0;
   }
   if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 6466862..9b7bcbd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -205,7 +205,7 @@
   IN      PCIe_ENGINE_CONFIG             *Engine
   )
 {
-  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) {
     return 0;
   }
   if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 8e5e3dd..27e7bce 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -205,7 +205,7 @@
   IN      PCIe_ENGINE_CONFIG             *Engine
   )
 {
-  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) {
     return 0;
   }
   if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {