Change in coreboot[master]: mb/google/asurada: Improve boot time by raising little CPU frequency

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49935 )

Change subject: mb/google/asurada: Improve boot time by raising little CPU frequency
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mb/google/asurada: Improve boot time by raising little CPU frequency

Raise little CPU to 2GHz at romstage to improve boot time.

BUG=b:177389446
TEST=observe boot time by `cbmem`
     Before: 1,062,359 us
     After: 907,458 us

Signed-off-by: Yidi Lin 
Change-Id: I723a916d7f708627525ef11e3c5ea0b381f269aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49935
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
---
M src/mainboard/google/asurada/romstage.c
M src/soc/mediatek/mt8192/Makefile.inc
2 files changed, 16 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c
index 47c1fb2..67b43e2 100644
--- a/src/mainboard/google/asurada/romstage.c
+++ b/src/mainboard/google/asurada/romstage.c
@@ -2,11 +2,14 @@

#include <arch/stages.h>
 #include <console/console.h>
+#include <delay.h>
 #include <fmap.h>
 #include <soc/dramc_param.h>
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
+#include <soc/mt6315.h>
 #include <soc/mt6359p.h>
+#include <soc/pll_common.h>

/* This must be defined in chromeos.fmd in same name and size. */
 #define CALIBRATION_REGION		"RW_DDR_TRAINING"
@@ -42,9 +45,20 @@
    .write_to_flash = &write_calibration_data_to_flash,
 };

+static void raise_little_cpu_freq(void)
+{
+	mt6359p_buck_set_voltage(MT6359P_SRAM_PROC2, 1000 * 1000);
+	mt6315_buck_set_voltage(MT6315_CPU, MT6315_BUCK_3, 925 * 1000);
+	udelay(200);
+	mt_pll_raise_little_cpu_freq(2000 * MHz);
+	mt_pll_raise_cci_freq(1400 * MHz);
+}
+
 void platform_romstage_main(void)
 {
    mt6359p_romstage_init();
+	mt6315_romstage_init();
+	raise_little_cpu_freq();
    mt_mem_init(&dparam_ops);
    mtk_mmu_after_dram();
 }
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index ad8b3d9..9d22ef2 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -36,10 +36,12 @@
 romstage-y += ../common/i2c.c i2c.c
 romstage-y += ../common/mmu_operations.c mmu_operations.c
 romstage-y += memory.c dramc_param.c ../common/memory_test.c
+romstage-y += ../common/pll.c pll.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c
 romstage-y += ../common/uart.c
 romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c
+romstage-y += mt6315.c
 romstage-y += mt6359p.c

ramstage-y += ../common/auxadc.c