Patch set updated for coreboot: 62ee959 Add DDR refresh config to pei data structure.

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4213

-gerrit

commit 62ee9597c5c34e2e3f51e22b6a094d574dd2f3cb
Author: Shawn Nematbakhsh 
Date:   Wed May 8 11:41:04 2013 -0700

Add DDR refresh config to pei data structure.

Allow platform customized DDR config, including forcing refresh rate to
    2x.

Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2
    Reviewed-on: https://gerrit.chromium.org/gerrit/50476
    Reviewed-by: Duncan Laurie 
    Tested-by: Shawn Nematbakhsh 
    Commit-Queue: Shawn Nematbakhsh 
---
 src/northbridge/intel/sandybridge/pei_data.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index d317515..5e0ff0f 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -121,6 +121,14 @@ struct pei_data
     * 2 2N
     */
    int nmode;
+	/* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows
+	 * for DIMM SPD data to specify whether double-rate is required for
+	 * extended operating temperature range.
+	 * 0 Enable double rate based upon temperature thresholds
+	 * 1 Normal rate
+	 * 2 Always enable double rate
+	 */
+	int ddr_refresh_rate_config;
 } __attribute__((packed));

#endif