Attention is currently required from: Hung-Te Lin, Xi Chen, Yidi Lin, Yu-Ping Wu.
Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83925?usp=email )
Change subject: soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA ......................................................................
soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA
- Turn off L2C SRAM and reconfigure as L2 cache: Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache.
- Configure DMA buffer in DRAM: Set DRAM DMA to be non-cacheable to load blob correctly.
TEST=build pass BUG=b:317009620
Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294 Signed-off-by: Jarried Lin jarried.lin@mediatek.corp-partner.google.com --- A src/soc/mediatek/common/l2c_ops.c M src/soc/mediatek/common/mmu_cmops.c M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8192/Makefile.mk M src/soc/mediatek/mt8195/Makefile.mk M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/l2c_ops.c M src/soc/mediatek/mt8196/soc.c 9 files changed, 88 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83925/1
diff --git a/src/soc/mediatek/common/l2c_ops.c b/src/soc/mediatek/common/l2c_ops.c new file mode 100644 index 0000000..46ce351 --- /dev/null +++ b/src/soc/mediatek/common/l2c_ops.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/mcucfg.h> +#include <soc/mmu_operations.h> + +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) + +void mtk_soc_disable_l2c_sram(void) +{ + unsigned long v; + + SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); + dsb(); + + __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); + v |= (0xf << 4); + __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); + dsb(); + + do { + __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); + } while (((v >> 0x4) & 0xf) != 0xf); + + SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); + dsb(); +} diff --git a/src/soc/mediatek/common/mmu_cmops.c b/src/soc/mediatek/common/mmu_cmops.c index 4b81a27..e102569 100644 --- a/src/soc/mediatek/common/mmu_cmops.c +++ b/src/soc/mediatek/common/mmu_cmops.c @@ -1,34 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <device/mmio.h> -#include <soc/mcucfg.h> -#include <soc/mmu_operations.h> #include <soc/symbols.h> - -DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) -DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) - -void mtk_soc_disable_l2c_sram(void) -{ - unsigned long v; - - SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0, - MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); - dsb(); - - __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); - v |= (0xf << 4); - __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); - dsb(); - - do { - __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); - } while (((v >> 0x4) & 0xf) != 0xf); - - SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0, - MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); - dsb(); -} +#include <soc/mmu_operations.h>
/* mtk_soc_after_dram is called in romstage */ void mtk_soc_after_dram(void) diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk index f637dcf..1282392 100644 --- a/src/soc/mediatek/mt8186/Makefile.mk +++ b/src/soc/mediatek/mt8186/Makefile.mk @@ -25,7 +25,7 @@ romstage-y += ../common/emi.c romstage-y += ../common/memory.c romstage-y += ../common/memory_test.c -romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ../common/l2c_ops.c romstage-y += ../common/mt6315.c mt6315.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c @@ -42,7 +42,7 @@ ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c -ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ../common/l2c_ops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk index 6a57da4..08b1532 100644 --- a/src/soc/mediatek/mt8188/Makefile.mk +++ b/src/soc/mediatek/mt8188/Makefile.mk @@ -23,7 +23,7 @@ romstage-y += ../common/emi.c romstage-y += ../common/memory.c romstage-y += ../common/memory_test.c -romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ../common/l2c_ops.c romstage-y += ../common/mt6315.c mt6315.c romstage-y += ../common/mt6359p.c mt6359p.c romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c @@ -45,7 +45,7 @@ ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c -ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ../common/l2c_ops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += ../common/mt6359p.c mt6359p.c ramstage-y += ../common/mtcmos.c mtcmos.c diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk index 4e35fe1..831dafa 100644 --- a/src/soc/mediatek/mt8192/Makefile.mk +++ b/src/soc/mediatek/mt8192/Makefile.mk @@ -22,7 +22,7 @@ romstage-y += ../common/dram_init.c romstage-y += ../common/dramc_param.c romstage-y += ../common/memory.c ../common/memory_test.c -romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ../common/l2c_ops.c romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif_spi.c pmif_spi.c @@ -41,7 +41,7 @@ ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c -ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ../common/l2c_ops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmif.c diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index d1c1920..935dc4b 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -25,7 +25,7 @@ romstage-y += emi.c romstage-y += ../common/memory.c romstage-y += ../common/memory_test.c -romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ../common/l2c_ops.c romstage-y += ../common/pll.c pll.c romstage-y += scp.c romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c @@ -53,7 +53,7 @@ ramstage-y += hdmi.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c -ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ../common/l2c_ops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += mt6360.c ramstage-y += ../common/mtcmos.c mtcmos.c diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 96aea39..97b4dd7 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -12,10 +12,12 @@ bootblock-y += ../common/mmu_operations.c
romstage-y += ../common/cbmem.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c l2c_ops.c romstage-y += emi.c
ramstage-y += emi.c ramstage-y += soc.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c l2c_ops.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8196/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8196/l2c_ops.c b/src/soc/mediatek/mt8196/l2c_ops.c new file mode 100644 index 0000000..4a032d5 --- /dev/null +++ b/src/soc/mediatek/mt8196/l2c_ops.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 9 + */ + +#include <device/mmio.h> +#include <soc/mmu_operations.h> + +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_FULLnHALF, 0) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 1) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 2) + +#define MP0_CLUSTER_CFG0 0x0C000060 +#define CLUST_DIS_VAL 0x3 +#define CLUST_DIS_SHIFT 0x4 + +void mtk_soc_disable_l2c_sram(void) +{ + unsigned long v; + + uint32_t *mp0_cluster_cfg0 = (void *)(MP0_CLUSTER_CFG0); + + SET32_BITFIELDS(mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); + dsb(); + + __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); + v |= (CLUST_DIS_VAL << CLUST_DIS_SHIFT); + __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); + dsb(); + + do { + __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); + } while (((v >> CLUST_DIS_SHIFT) & CLUST_DIS_VAL) != CLUST_DIS_VAL); + + SET32_BITFIELDS(mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); + + SET32_BITFIELDS(mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_FULLnHALF, 0); + + dsb(); +} diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index b77735c..ddbf0f9 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -3,6 +3,7 @@ #include <device/device.h> #include <soc/emi.h> #include <symbols.h> +#include <soc/mmu_operations.h>
static void soc_read_resources(struct device *dev) { @@ -11,6 +12,7 @@
static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); }
static struct device_operations soc_ops = {