Change in coreboot[master]: src/soc/intel/braswell/include.soc/irq.h: Set bit 7 if PIRQ register ...

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29393

Change subject: src/soc/intel/braswell/include.soc/irq.h: Set bit 7 if PIRQ register to disable
......................................................................

src/soc/intel/braswell/include.soc/irq.h: Set bit 7 if PIRQ register to disable

PIRQ register is not set to disabled.
Set bit 7 of the PIRQ registers to disable the PIRQ

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/include/soc/irq.h
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29393/1

diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h
index 4375c20..a232755 100644
--- a/src/soc/intel/braswell/include/soc/irq.h
+++ b/src/soc/intel/braswell/include/soc/irq.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -142,7 +143,7 @@

/* PIC IRQ settings. */
-#define PIRQ_PIC_IRQDISABLE		0x0
+#define PIRQ_PIC_IRQDISABLE		0x80
 #define PIRQ_PIC_IRQ3			0x3
 #define PIRQ_PIC_IRQ4			0x4
 #define PIRQ_PIC_IRQ5			0x5