[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC

[Subrata Banik (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )

Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
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Patch Set 67:

(5 comments)

Patchset:

PS46:
> Thx. Yes. I do plan to have this change in https://review.coreboot. […]

Acknowledged

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83789/comment/897f90f2_c434d5de?usp... :
PS17, Line 263: 	  Since Lunarlake, OS pinctrl no long provides SOC GPIO pincntrl info.
              : 	  Rather, firmware is responsible for providing such info via APCI.
              : 	  Firmware can provide entire PADs or excluding those non GPP_[group]_[number]
              : 	  at the end of each community.
> > Subrata, […]

Acknowledged

File src/soc/intel/pantherlake/gpio.c:

https://review.coreboot.org/c/coreboot/+/83789/comment/b5d554f7_ee359622?usp... :
PS17, Line 73: 		.num_groups = ARRAY_SIZE(ptl_community0_groups),
> Yes, only cpu_port needs to be changed. […]

Acknowledged

File src/soc/intel/pantherlake/include/soc/gpio_defs.h:

https://review.coreboot.org/c/coreboot/+/83789/comment/1ed83ec9_3fa22c20?usp... :
PS49, Line 261: GPP_CPUJTAG_OFFSET
> This is used in gpio.asl.

Acknowledged

File src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h:

https://review.coreboot.org/c/coreboot/+/83789/comment/4d9a6353_d171286d?usp... :
PS17, Line 544: #define GPP_VGPIO0		246
> > Let's the feedback on lack of info in PTL EDS and route this to the proper owner for change. […]

Acknowledged