[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

[Shuo Liu (Code Review)]

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Held, Felix Singer, Frans Hendriks, Jérémy Compostella, Patrick Rudolph, Paul Menzel, [e-mail].

Shuo Liu has posted comments on this change by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email )

Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
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Patch Set 60: Code-Review+1

(6 comments)

File src/soc/intel/snowridge/acpi.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/4eaf1bae_bca5460e?usp... :
PS60, Line 94: 		/* PCH PCIe root port needs further swizzle. */
Not sure the root port itself needs such pin swizzle or not (though I agree its child device's intx message needs such transformation).

https://review.coreboot.org/c/coreboot/+/83321/comment/dbe62fd7_31918f30?usp... :
PS60, Line 115: 	intel_write_pci_PRT(scope, pin_irq_map, map_count, &pirq_map);
The scope could be obtained from domain's device path, e.g. acpi_device_acope()

https://review.coreboot.org/c/coreboot/+/83321/comment/e1b2d794_30eba74d?usp... :
PS60, Line 127: 	/* Generating accelerator domains dynamically since they are SKU-dependent. */
Maybe add a comment that pch domain (domain0) is in dsdt

https://review.coreboot.org/c/coreboot/+/83321/comment/dd299d59_3d3ded73?usp... :
PS60, Line 280: 		if (dev == DEV_PTR(dlb_sa)) {
If using devicetree ptr in soc codes, there should be a soc layer devicetree.cb to be consistent.

https://review.coreboot.org/c/coreboot/+/83321/comment/7a6e963b_52aad638?usp... :
PS60, Line 333: 	struct device *dev = PCH_DEV_XHCI;
Not sure if this could be represented as a devicetree ptr, thus to reduce the types of dev reference overall.

File src/soc/intel/snowridge/lpc.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/c75c76a3_23349e8b?usp... :
PS60, Line 47: 			swizzle_pin = get_pci_irq_pins(dev, &bridge);
Can this code working with multiple pcie bridge layers?