Change in coreboot[master]: sb/intel/bd82x6x: Set up LPC Generic Memory Range register

[Bill XIE (Code Review)]

Attention is currently required from: Patrick Rudolph.
Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52368 )

Change subject: sb/intel/bd82x6x: Set up LPC Generic Memory Range register
......................................................................

sb/intel/bd82x6x: Set up LPC Generic Memory Range register

Following how it is handled on lynxpoint.
(In http://review.coreboot.org/2682 )

Signed-off-by: Bill XIE 
Change-Id: If0cb536441032b462f23e65092da8ab0a4795a78
---
M src/southbridge/intel/bd82x6x/lpc.c
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/52368/1

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index ee416c1..341fad5 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -617,6 +617,19 @@
    	res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE |
    			 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
    }
+
+	/* Check LPC Memory Decode register. */
+	uint32_t reg = pci_read_config32(dev, LGMR);
+	if (reg & 1) {
+		reg &= ~0xffff;
+		if (reg < IO_APIC_ADDR) {
+			res = new_resource(dev, LGMR);
+			res->base = reg;
+			res->size = 16 * 1024;
+			res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+				     IORESOURCE_FIXED | IORESOURCE_RESERVE;
+		}
+	}
 }

static void pch_lpc_enable(struct device *dev)