Change in coreboot[master]: device/pci_device.c: Improve pci_bridge_route() readability

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans, Nico Huber, Angel Pons.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59131 )

Change subject: device/pci_device.c: Improve pci_bridge_route() readability
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Patch Set 3:

(2 comments)

File src/device/pci_device.c:

https://review.coreboot.org/c/coreboot/+/59131/comment/ee899fdc_f76773d6 
PS1, Line 1337: u32 raw;
              : 		struct {
              : 			u8 primary;
              : 			u8 secondary;
              : 			u8 subordinate;
              : 			u8 _latency;
              : 		} __packed;
> Depends on the implementation of pci_write_config32(). IMHO, it should be
> aware of the endianness and then converting the word here locally would
> actually break things.
>
> Usually, I would recommend explicit serialization / de-serialization. But
> in this case don't we actually want to write 3 registers? Would it hurt to
> use pci_write_config8()?
>
> For readability, I'd simply use plain, simple variables, e.g.
> u8 primary, secondary, subordinate;
>
> if (state == PCI_ROUTE_CLOSE) {
>         primary     = 0x00;
>         secondary   = 0xff;
>         subordinate = 0xfe;
> } else if (...) {
>         ...
> } else {
>         ...
> }
>
> Then, either serialize the results into a u32 in a single spot and use
> pci_write_config32(), or just use pci_write_config8() three times.

Thanks.
Went for the 3 config writes, because it makes it easier to search for.

File src/device/pci_device.c:

https://review.coreboot.org/c/coreboot/+/59131/comment/c1f455b7_f3ea1607 
PS2, Line 1351: 
              : 		buses.primary = 0xff;
              : 		buses.secondary = 0xfe;
> Should be `secondary` and `subordinate`, right?

Uh I missed the << 8 probably. Fixed it.