Change in coreboot[master]: soc/intel/jsl: Add CdClock config - coreboot-gerrit

17 Dec 2021


      Attention is currently required from: Jamie Chen, Simon Yang, Kane Chen, Patrick Rudolph.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )
Change subject: soc/intel/jsl: Add CdClock config
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Patch Set 8:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60009/comment/488e5b2c_b66b0fee 
PS7, Line 9: Jasperlake
Jasper Lake.
https://review.coreboot.org/c/coreboot/+/60009/comment/0540350d_b86b0289 
PS7, Line 10: 
Why set it to 0xff?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
Gerrit-Change-Number: 60009
Gerrit-PatchSet: 8
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