Change in coreboot[master]: soc/intel/xeon_sp: Lock PAM and SMRAM registers

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47168 )

Change subject: soc/intel/xeon_sp: Lock PAM and SMRAM registers
......................................................................

soc/intel/xeon_sp: Lock PAM and SMRAM registers

The CedarIsland FSP Integration recommends locking down some things.

Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47168
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/cpx/chip.c
1 file changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 592a316..a3076a8 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -68,6 +68,18 @@
 {
    /* Lock SBI */
    pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK);
+
+	/* LOCK PAM */
+	pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0);
+
+	/*
+	 * LOCK SMRAM
+	 * According to the CedarIsland FSP Integration Guide this needs to
+	 * be done with legacy 0xCF8/0xCFC IO ops.
+	 */
+	uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88);
+	pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4));
+
    p2sb_hide();

set_bios_init_completion();