Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Yu-Ping Wu.
Yidi Lin has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )
Change subject: soc/mediatek/common: Fix eMMC clock
......................................................................
Patch Set 8:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/b59cae2c_7b648eb6?usp... :
PS8, Line 9: start
starts
https://review.coreboot.org/c/coreboot/+/84298/comment/5a9410ec_5d91a342?usp... :
PS8, Line 9: Mediatek SOC start operating at eMMC clock around 2 MHz right after
: power-on. In JEDEC spec, this period is 400 kHz or less.
If you insist on using your own commit messages, please make sure they're grammatically correct.
https://review.coreboot.org/c/coreboot/+/84298/comment/f46be3c3_b388db2b?usp... :
PS8, Line 10: 400 kHz
this is not used to describe the time interval.
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