Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45916 )
Change subject: nb/intel/x4x/memmap.c: Use `postcar_enable_tseg_cache` ......................................................................
nb/intel/x4x/memmap.c: Use `postcar_enable_tseg_cache`
Also correct comments and clean up cosmetics of the function.
Change-Id: I99dfe339c46f1ab4f5bbbd8ae4368e43cd169fc4 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/x4x/memmap.c 1 file changed, 5 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45916/1
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index aa737f3..0c62fdc 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -124,12 +124,10 @@ { uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ + /* Cache 8 MiB region below the top of RAM to cover CBMEM */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); }
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45916 )
Change subject: nb/intel/x4x/memmap.c: Use `postcar_enable_tseg_cache` ......................................................................
Patch Set 2: Code-Review-2
On hold until the purpose of caching what is marked as TSEG is clear. This might have to do with the stage cache.
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45916 )
Change subject: nb/intel/x4x/memmap.c: Use `postcar_enable_tseg_cache` ......................................................................
Abandoned