[S] Change in coreboot[master]: mb/google/brya/var/lisbon: Disable thunderbolt ports

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68916 )

Change subject: mb/google/brya/var/lisbon: Disable thunderbolt ports
......................................................................

mb/google/brya/var/lisbon: Disable thunderbolt ports

Lisbon doesn't support thunderbolt.

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu 
Change-Id: Iac44315d000c3c0c572efb00e877d039e0308455
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68916
Reviewed-by: Nick Vaccaro 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/brya/variants/lisbon/overridetree.cb
1 file changed, 26 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb
index 23c3461..fc285639 100644
--- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb
+++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb
@@ -150,13 +150,12 @@
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    	end
-		device ref tcss_dma0 on
-			chip drivers/intel/usb4/retimer
-				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
-				use tcss_usb3_port1 as dfp[0].typec_port
-				device generic 0 on end
-			end
-		end
+		device ref tbt_pcie_rp0 off end
+		device ref tbt_pcie_rp1 off end
+		device ref tbt_pcie_rp2 off end
+
+		device ref tcss_dma0 off end
+		device ref tcss_dma1 off end
    	device ref cnvi_wifi on
    		chip drivers/wifi/generic
    			register "wake" = "GPE0_PME_B0"