Change in coreboot[master]: amd/common/psp: Flush buffer before commands

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22849

Change subject: amd/common/psp: Flush buffer before commands
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amd/common/psp: Flush buffer before commands

The PSP and x86 caches are not coherent.  Although the PSP can read
information from the x86 cache, its updates to the command-response
buffer go to DRAM.

Flush the cacheline(s) containing the command-response buffer prior
to issuing the command, and ensure it is accurately read after the
completion.

BUG=b:67309243

Change-Id: I2aa7bbddcb2197aeb9f92683465d014ec97ac64c
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/common/block/psp/psp.c
1 file changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/22849/1

diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c
index 8035a61..e9f9da8 100644
--- a/src/soc/amd/common/block/psp/psp.c
+++ b/src/soc/amd/common/block/psp/psp.c
@@ -15,6 +15,8 @@

#include <arch/io.h>
 #include <arch/early_variables.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/cache.h>
 #include <cbfs.h>
 #include <region_file.h>
 #include <timer.h>
@@ -173,6 +175,28 @@
 }

/*
+ * The PSP's cache is not fully coherent with the x86's and PSP writes to the
+ * buffer go to DRAM.  This flushes the buffer so that once the x86 reads the
+ * buffer again, it refills modified values from DRAM.
+ *
+ * This function should be called on an as-needed basis depending on the
+ * command.  Some commands do not use a buffer.
+ */
+static void flush_buffer(void *buffer, size_t sz)
+{
+	int i;
+	u8 *b = (u8 *)buffer;
+	int lines = ALIGN_UP((uintptr_t)buffer + sz, CACHELINE_SIZE)
+				- ALIGN_DOWN((uintptr_t)buffer, CACHELINE_SIZE);
+	lines /= CACHELINE_SIZE;
+
+	for (i = 0 ; i < lines ; i++) {
+		mfence();
+		clflush(b + i * 64);
+	}
+}
+
+/*
  * Notify the PSP that DRAM is present.  Upon receiving this command, the PSP
  * will load its OS into fenced DRAM that is not accessible to the x86 cores.
  */
@@ -187,6 +211,7 @@

printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... ");

+	flush_buffer(&buffer, sizeof(buffer));
    cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer);

/* buffer's status shouldn't change but report it if it does */
@@ -217,6 +242,7 @@

printk(BIOS_DEBUG, "PSP: Notify that POST is finishing... ");

+	flush_buffer(&buffer, sizeof(buffer));
    cmd_status = send_psp_command(MBOX_BIOS_CMD_BOOT_DONE, &buffer);

/* buffer's status shouldn't change but report it if it does */