Change in coreboot[master]: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40385 )

Change subject: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
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Patch Set 21:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40385/21/src/soc/intel/xeon_sp/cpx/... 
File src/soc/intel/xeon_sp/cpx/romstage.c:

https://review.coreboot.org/c/coreboot/+/40385/21/src/soc/intel/xeon_sp/cpx/... 
PS21, Line 24: 	arch_upd->StackBase = (void *) 0xfe930000;
Can we do this as part of the device tree and not hardcode the configuration?