[S] Change in coreboot[main]: security/intel/txt: Make romstage init work on SOC_INTEL platforms

[Michał Żygowski (Code Review)]

Attention is currently required from: Michał Kopeć, Michał Żygowski.

Michał Żygowski has uploaded a new patch set (#4) to the change originally created by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82694?usp=email )

Change subject: security/intel/txt: Make romstage init work on SOC_INTEL platforms
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security/intel/txt: Make romstage init work on SOC_INTEL platforms

Use Intel SOC common PMC block to clear SLP_TYP field in ACPI PM1.
It will enable the intel_txt_romstage_init to work on soc/skylake
and soc/cannonlake. Newer SOCs like TigerLake already have CBnT
and run ACM from FIT, so do not need to call intel_txt_romstage_init.

TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled.

Change-Id: I892c9eff16d51adc94b75c9ef9f0f1be4f50bada
Signed-off-by: Michał Żygowski 
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M src/security/intel/txt/romstage.c
1 file changed, 15 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/82694/4