New patch to review for coreboot: glados: enable SMBus device

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11181

-gerrit

commit 7e059158139e5c54a448441a52593338300292ac
Author: Aaron Durbin 
Date:   Tue Aug 4 11:03:00 2015 -0500

glados: enable SMBus device

In order to run with the debug FSP the SMBus device needs
    to be enabled. Additionally, the TCO block lives within
    the SMBus device so if TCO is to be employed then the
    SMBus device needs to be enabled as a prerequisite.

BUG=chrome-os-partner:42407
    BRANCH=None
    TEST=Buit and booted into kernel.

Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89
    Original-Signed-off-by: Aaron Durbin 
    Original-Reviewed-on: https://chromium-review.googlesource.com/290364
    Original-Reviewed-by: Bernie Thompson 
    Original-Reviewed-by: Robbie Zhang

Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2
    Signed-off-by: Aaron Durbin 
---
 src/mainboard/google/glados/devicetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index b48556f..2e1cae7 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -44,7 +44,7 @@ chip soc/intel/skylake
    register "IshEnable" = "0"
    register "XdciEnable" = "0"
    register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "0"
+	register "SmbusEnable" = "1"
    register "Cio2Enable" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
@@ -102,7 +102,7 @@ chip soc/intel/skylake
    	end # LPC Interface
    	device pci 1f.2 on  end # Power Management Controller
    	device pci 1f.3 on  end # Intel High Definition Audio
-		device pci 1f.4 off end # SMBus Controller
+		device pci 1f.4 on  end # SMBus Controller
    	device pci 1f.5 on  end # PCH SPI
    	device pci 1f.6 off end # GbE Controller
    end