Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36248 )
Change subject: soc/intel/tigerlake: Update GPIOs for Tigerlake SOC ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36248/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36248/3//COMMIT_MSG@30 PS3, Line 30: BUG=None
its not broken rather delta over ICL for TGL.which is expected to be different . […]
Please stop talking nonsense. If the register offset is completly different, then the TGL commit is technically broken.
https://review.coreboot.org/c/coreboot/+/36248/3//COMMIT_MSG@32 PS3, Line 32: TEST=None
this is not good CL without test ?
How you know it doesn't ... "introduce deltas"? Why don't you test code contributed to coreboot?
https://review.coreboot.org/c/coreboot/+/36248/3/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/36248/3/src/soc/intel/tigerlake/inc... PS3, Line 21: #define ABASE 0x40
with PMC revision change its expected that some reg offset moves around. so this is to capture that.
please document PMC revision and datasheet used for reference
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Patrick Rudolph (Code Review)