Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52865 )
Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO ......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52865/comment/0d237070_67558242 PS1, Line 9: We need to configure CPU PCIE root port related gpios in early : boot block stage for CPU root ports to work.
Can you please add the reason why CPU root ports do not work if the pads are configured later on i. […]
Hi Furquan,
FSP is configuring all CPU PCIe root ports in romstage and this GPIO configuration is needed for FSP to configure other PCIe registers. This is the reason if we do it in later stage, we still see CPU PCIe root port init failure.