Change in coreboot[master]: Inicial device tree for Microtech etabpro Platform Intel GLK Tablet w...
Miroslaw Kocur has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39268 )
Change subject: Inicial device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard ......................................................................
Inicial device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard
Based on clean GLK tree Not working so far
Changes : - Cleaning code
Change-Id: I726dbb3dc036cc30ff3d842f8ffbf76604375dbb Signed-off-by: Miroslaw Kocur mirek190@gmail.com --- M src/mainboard/microtech/etabpro/Kconfig M src/mainboard/microtech/etabpro/Kconfig.name M src/mainboard/microtech/etabpro/Makefile.inc D src/mainboard/microtech/etabpro/boardid.c M src/mainboard/microtech/etabpro/bootblock.c D src/mainboard/microtech/etabpro/chromeos.c M src/mainboard/microtech/etabpro/dsdt.asl D src/mainboard/microtech/etabpro/ec.c D src/mainboard/microtech/etabpro/ec.h M src/mainboard/microtech/etabpro/gpio.c M src/mainboard/microtech/etabpro/mainboard.c M src/mainboard/microtech/etabpro/memory.c D src/mainboard/microtech/etabpro/nhlt.c M src/mainboard/microtech/etabpro/romstage.c D src/mainboard/microtech/etabpro/smihandler.c 15 files changed, 17 insertions(+), 440 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/39268/1
diff --git a/src/mainboard/microtech/etabpro/Kconfig b/src/mainboard/microtech/etabpro/Kconfig index 3510021..6c91dff 100644 --- a/src/mainboard/microtech/etabpro/Kconfig +++ b/src/mainboard/microtech/etabpro/Kconfig @@ -1,7 +1,7 @@ if BOARD_MICROTECH_ETABPRO
-config BOARD_INTEL_BASEBOARD_GLKRVP - def_bool n +config BOARD_SPECIFIC_OPTIONS + def_bool y select SOC_INTEL_GLK select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC @@ -9,22 +9,13 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE - select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - select SOC_ESPI # Blobs # select NEED_IFWI # select HAVE_IFD_BIN -# config for GLK CHROME EC - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ESPI - select VBOOT_LID_SWITCH - select EC_GOOGLE_CHROMEEC_SWITCHES # config for GLK INTEL_EC # Not sure is VBOOT_NO_BOARD_SUPPORT is needed to work coreboot on GLK. Without it we got error if I choose GLK INTEL_EC... -# select EC_ACPI + select EC_ACPI # select VBOOT_NO_BOARD_SUPPORT
@@ -40,38 +31,25 @@ def_bool y select SYSTEM_TYPE_LAPTOP
-config VBOOT - select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN +#config VBOOT +# select HAS_RECOVERY_MRC_CACHE +# select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/etab.fmd"
-config CHROMEOS - bool - default y - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - config MAINBOARD_DIR string default "microtech/etabpro"
-config VARIANT_DIR - string - default "glkrvp" - -config DEVICETREE - string - default "devicetree.cb" - config MAINBOARD_PART_NUMBER string default "etabpro"
config MAINBOARD_FAMILY string - default "Intel_Glkrvp" + default "Intel_GLK"
config MAX_CPUS int @@ -81,18 +59,8 @@ int default 2
-config IS_GLK_RVP_1 - bool "Is this RVP1?" - default n - config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE bool default y
-config INCLUDE_NHLT_BLOBS - bool "Include blobs for audio" - select NHLT_DMIC_2CH_16B - select NHLT_DMIC_4CH_16B - select NHLT_MAX98357 - endif # BOARD_MICROTECH_ETABPRO diff --git a/src/mainboard/microtech/etabpro/Kconfig.name b/src/mainboard/microtech/etabpro/Kconfig.name index bc505e5..ab1d1e7 100644 --- a/src/mainboard/microtech/etabpro/Kconfig.name +++ b/src/mainboard/microtech/etabpro/Kconfig.name @@ -1,4 +1,2 @@ config BOARD_MICROTECH_ETABPRO bool "etabpro" - select BOARD_INTEL_BASEBOARD_GLKRVP - select BASEBOARD_GLKRVP_LAPTOP diff --git a/src/mainboard/microtech/etabpro/Makefile.inc b/src/mainboard/microtech/etabpro/Makefile.inc index 9835dfb..3fafe9c 100644 --- a/src/mainboard/microtech/etabpro/Makefile.inc +++ b/src/mainboard/microtech/etabpro/Makefile.inc @@ -1,21 +1,10 @@ bootblock-y += bootblock.c -bootblock-y += ec.c
-romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += boardid.c - -ramstage-y += boardid.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += ec.c ramstage-y += mainboard.c
-verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c - bootblock-y += gpio.c romstage-y += memory.c -ramstage-y += boardid.c ramstage-y += gpio.c -ramstage-y += nhlt.c + smm-y += gpio.c
diff --git a/src/mainboard/microtech/etabpro/boardid.c b/src/mainboard/microtech/etabpro/boardid.c deleted file mode 100644 index 0923e9d..0000000 --- a/src/mainboard/microtech/etabpro/boardid.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "variants.h" -#include <boardid.h> -#include <ec/google/chromeec/ec.h> - -int variant_board_id(void) -{ - MAYBE_STATIC_NONZERO uint32_t id = BOARD_ID_INIT; - - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - if (id == BOARD_ID_INIT) { - if (google_chromeec_get_board_version(&id)) - id = BOARD_ID_UNKNOWN; - } - return id; - } else { - return 0; - } -} diff --git a/src/mainboard/microtech/etabpro/bootblock.c b/src/mainboard/microtech/etabpro/bootblock.c index 3d27050..1098af5 100644 --- a/src/mainboard/microtech/etabpro/bootblock.c +++ b/src/mainboard/microtech/etabpro/bootblock.c @@ -15,10 +15,9 @@
#include "variants.h" #include <bootblock_common.h> -#include <ec/ec.h> #include <intelblocks/lpc_lib.h> #include <soc/gpio.h> -#include "ec.h" +
void bootblock_mainboard_init(void) { @@ -28,5 +27,5 @@ lpc_configure_pads(); pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); - mainboard_ec_init(); +// mainboard_ec_init(); } diff --git a/src/mainboard/microtech/etabpro/chromeos.c b/src/mainboard/microtech/etabpro/chromeos.c deleted file mode 100644 index f59b462..0000000 --- a/src/mainboard/microtech/etabpro/chromeos.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "variants.h" -#include <boot/coreboot_tables.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> -#include "gpio.h" - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {-1, ACTIVE_HIGH, 0, "EC in RW"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_write_protect_state(void) -{ - return 0; -} - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - -int __weak get_lid_switch(void) -{ - return -1; -} diff --git a/src/mainboard/microtech/etabpro/dsdt.asl b/src/mainboard/microtech/etabpro/dsdt.asl index c1c0924..89a1ac8 100644 --- a/src/mainboard/microtech/etabpro/dsdt.asl +++ b/src/mainboard/microtech/etabpro/dsdt.asl @@ -13,7 +13,6 @@ * GNU General Public License for more details. */
-#include "ec.h" #include "gpio.h"
#include <arch/acpi.h> @@ -28,8 +27,6 @@ { /* global NVS and variables */ #include <soc/intel/apollolake/acpi/globalnvs.asl> - - /* CPU */ #include <cpu/intel/common/acpi/cpu.asl>
Scope (_SB) { @@ -41,28 +38,14 @@ } }
- /* Chrome OS specific */ - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - #include <southbridge/intel/common/acpi/sleepstates.asl> - - /* Chrome OS Embedded Controller */ - Scope (_SB.PCI0.LPCB) - { - /* ACPI code for EC SuperIO functions */ - #include <ec/google/chromeec/acpi/superio.asl> - /* ACPI code for EC functions */ - #include <ec/google/chromeec/acpi/ec.asl> - } - /* Dynamic Platform Thermal Framework */ Scope (_SB) { /* Per board variant specific definitions. */ - #include "dptf.asl" +// #include "dptf.asl" /* Include soc specific DPTF changes */ - #include <soc/intel/apollolake/acpi/dptf.asl> +// #include <soc/intel/apollolake/acpi/dptf.asl> /* Include common dptf ASL files */ - #include <soc/intel/common/acpi/dptf/dptf.asl> +// #include <soc/intel/common/acpi/dptf/dptf.asl> } } diff --git a/src/mainboard/microtech/etabpro/ec.c b/src/mainboard/microtech/etabpro/ec.c deleted file mode 100644 index 9d44ea9..0000000 --- a/src/mainboard/microtech/etabpro/ec.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <ec/ec.h> -#include <ec/google/chromeec/ec.h> -#include <intelblocks/lpc_lib.h> -#include "ec.h" - -static void ramstage_ec_init(void) -{ - const struct google_chromeec_event_info info = { - .log_events = MAINBOARD_EC_LOG_EVENTS, - .sci_events = MAINBOARD_EC_SCI_EVENTS, - .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, - .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, - .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, - }; - - printk(BIOS_ERR, "mainboard: EC init\n"); - - google_chromeec_events_init(&info, acpi_is_wakeup_s3()); -} - -static void bootblock_ec_init(void) -{ - uint16_t ec_ioport_base; - size_t ec_ioport_size; - - /* - * Set up LPC decoding for the ChromeEC I/O port ranges: - * - Ports 62/66, 60/64, and 200->208 - * - ChromeEC specific communication I/O ports. - */ - lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 - | LPC_IOE_LGE_200); - google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size); - lpc_open_pmio_window(ec_ioport_base, ec_ioport_size); -} - -void mainboard_ec_init(void) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - if (ENV_RAMSTAGE) - ramstage_ec_init(); - else if (ENV_BOOTBLOCK) - bootblock_ec_init(); - } else if (ENV_BOOTBLOCK) { - /* - * Set up LPC decoding for the ChromeEC I/O port ranges: - * - Ports 62/66, 60/64, and 200->208 - * - ChromeEC specific communication I/O ports. - */ - lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 - | LPC_IOE_LGE_200); - } - - if (CONFIG(GLK_INTEL_EC)) { - printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n"); - outb(0xaa, 0x66); - printk(BIOS_INFO, "Hack to turn on the CPU fan\n"); - outb(0x81, 0x66); - outb(0x44, 0x62); - outb(0x32, 0x62); - /* Need delay here, hence second outb */ - outb(0x32, 0x62); - outb(0x1a, 0x66); - } -} diff --git a/src/mainboard/microtech/etabpro/ec.h b/src/mainboard/microtech/etabpro/ec.h deleted file mode 100644 index d31d35a..0000000 --- a/src/mainboard/microtech/etabpro/ec.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BASEBOARD_EC_H -#define BASEBOARD_EC_H - -#include <ec/google/chromeec/ec_commands.h> - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#endif diff --git a/src/mainboard/microtech/etabpro/gpio.c b/src/mainboard/microtech/etabpro/gpio.c index 8dedbe0..71c0d16 100644 --- a/src/mainboard/microtech/etabpro/gpio.c +++ b/src/mainboard/microtech/etabpro/gpio.c @@ -12,9 +12,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the * GNU General Public License for more details. */ - -#include <gpio.h> #include "variants.h" +#include <gpio.h> #include <commonlib/helpers.h>
/* diff --git a/src/mainboard/microtech/etabpro/mainboard.c b/src/mainboard/microtech/etabpro/mainboard.c index af0b1a3..15e81a9 100644 --- a/src/mainboard/microtech/etabpro/mainboard.c +++ b/src/mainboard/microtech/etabpro/mainboard.c @@ -12,33 +12,25 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - #include <arch/acpi.h> #include "variants.h" -#include <boardid.h> #include <console/console.h> #include <device/device.h> #include <ec/ec.h> #include <nhlt.h> #include <soc/gpio.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" #include "gpio.h"
static void mainboard_init(void *chip_info) { - int boardid; const struct pad_config *pads; size_t num;
- boardid = board_id(); - printk(BIOS_INFO, "Board ID: %d\n", boardid); - pads = variant_gpio_table(&num); gpio_configure_pads(pads, num);
- mainboard_ec_init(); +// mainboard_ec_init(); }
static unsigned long mainboard_write_acpi_tables( @@ -55,7 +47,7 @@ if (nhlt == NULL) return start_addr;
- variant_nhlt_init(nhlt); +// variant_nhlt_init(nhlt);
end_addr = nhlt_soc_serialize(nhlt, start_addr);
diff --git a/src/mainboard/microtech/etabpro/memory.c b/src/mainboard/microtech/etabpro/memory.c index 3f738d6..2a4c43e 100644 --- a/src/mainboard/microtech/etabpro/memory.c +++ b/src/mainboard/microtech/etabpro/memory.c @@ -12,7 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - #include "variants.h" #include <gpio.h> #include <soc/meminit.h> diff --git a/src/mainboard/microtech/etabpro/nhlt.c b/src/mainboard/microtech/etabpro/nhlt.c deleted file mode 100644 index 73cae3d..0000000 --- a/src/mainboard/microtech/etabpro/nhlt.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "variants.h" -#include <console/console.h> -#include <nhlt.h> -#include <soc/nhlt.h> - -void __weak variant_nhlt_init(struct nhlt *nhlt) -{ - /* 1-dmic configuration */ - if (CONFIG(NHLT_DMIC_1CH_16B) && - !nhlt_soc_add_dmic_array(nhlt, 1)) - printk(BIOS_ERR, "Added 1CH DMIC array.\n"); - /* 2-dmic configuration */ - if (CONFIG(NHLT_DMIC_2CH_16B) && - !nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Added 2CH DMIC array.\n"); - /* 4-dmic configuration */ - if (CONFIG(NHLT_DMIC_4CH_16B) && - !nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Added 4CH DMIC array.\n"); - - /* Dialog for Headset codec. - * Headset codec is bi-directional but uses the same configuration - * settings for render and capture endpoints. - */ - if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2)) - printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); - - /* MAXIM Smart Amps for left and right speakers. */ - if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); -} diff --git a/src/mainboard/microtech/etabpro/romstage.c b/src/mainboard/microtech/etabpro/romstage.c index 6cf48c3..2c42ee6 100644 --- a/src/mainboard/microtech/etabpro/romstage.c +++ b/src/mainboard/microtech/etabpro/romstage.c @@ -12,9 +12,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <string.h> #include "variants.h" -#include <boardid.h> +#include <string.h> #include <soc/meminit.h> #include <soc/romstage.h>
diff --git a/src/mainboard/microtech/etabpro/smihandler.c b/src/mainboard/microtech/etabpro/smihandler.c deleted file mode 100644 index edabd49..0000000 --- a/src/mainboard/microtech/etabpro/smihandler.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include "variants.h" -#include <cpu/x86/smm.h> -#include <ec/google/chromeec/smm.h> -#include <intelblocks/smihandler.h> -#include <soc/pm.h> -#include <soc/gpio.h> -#include "ec.h" -#include "gpio.h" - -void mainboard_smi_gpi_handler(const struct gpi_status *sts) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) - if (gpi_status_get(sts, EC_SMI_GPI)) - chromeec_smi_process_events(); -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_sleep_gpio_table(&num); - gpio_configure_pads(pads, num); - - if (CONFIG(EC_GOOGLE_CHROMEEC)) - chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, - MAINBOARD_EC_S5_WAKE_EVENTS); -} - -int mainboard_smi_apmc(u8 apmc) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) - chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, - MAINBOARD_EC_SMI_EVENTS); - return 0; -} - -void mainboard_smi_espi_handler(void) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) - chromeec_smi_process_events(); -}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39268 )
Change subject: Inicial device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39268/1/src/mainboard/microtech/eta... File src/mainboard/microtech/etabpro/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39268/1/src/mainboard/microtech/eta... PS1, Line 30: // mainboard_ec_init(); please, no space before tabs
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39268
to look at the new patch set (#2).
Change subject: Inicial device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard ......................................................................
Inicial device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard
Based on clean GLK tree Not working so far
Changes : - Cleaning code
Change-Id: I726dbb3dc036cc30ff3d842f8ffbf76604375dbb Signed-off-by: Miroslaw Kocur mirek190@gmail.com --- D src/mainboard/google/octopus/Kconfig D src/mainboard/google/octopus/Kconfig.name D src/mainboard/google/octopus/Makefile.inc D src/mainboard/google/octopus/board_info.txt D src/mainboard/google/octopus/bootblock.c D src/mainboard/google/octopus/chromeos.c D src/mainboard/google/octopus/chromeos.fmd D src/mainboard/google/octopus/dsdt.asl D src/mainboard/google/octopus/ec.c D src/mainboard/google/octopus/mainboard.c D src/mainboard/google/octopus/mainboard_misc.c D src/mainboard/google/octopus/romstage.c D src/mainboard/google/octopus/smihandler.c D src/mainboard/google/octopus/variants/ampton/Makefile.inc D src/mainboard/google/octopus/variants/ampton/gpio.c D src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/ampton/include/variant/ec.h D src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h D src/mainboard/google/octopus/variants/ampton/overridetree.cb D src/mainboard/google/octopus/variants/baseboard/Makefile.inc D src/mainboard/google/octopus/variants/baseboard/devicetree.cb D src/mainboard/google/octopus/variants/baseboard/gpio.c D src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl D src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h D src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h D src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h D src/mainboard/google/octopus/variants/baseboard/memory.c D src/mainboard/google/octopus/variants/baseboard/nhlt.c D src/mainboard/google/octopus/variants/bloog/Makefile.inc D src/mainboard/google/octopus/variants/bloog/gpio.c D src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/bloog/include/variant/ec.h D src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h D src/mainboard/google/octopus/variants/bloog/overridetree.cb D src/mainboard/google/octopus/variants/bloog/variant.c D src/mainboard/google/octopus/variants/bobba/Makefile.inc D src/mainboard/google/octopus/variants/bobba/gpio.c D src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/bobba/include/variant/ec.h D src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h D src/mainboard/google/octopus/variants/bobba/overridetree.cb D src/mainboard/google/octopus/variants/bobba/variant.c D src/mainboard/google/octopus/variants/casta/Makefile.inc D src/mainboard/google/octopus/variants/casta/gpio.c D src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/casta/include/variant/ec.h D src/mainboard/google/octopus/variants/casta/include/variant/gpio.h D src/mainboard/google/octopus/variants/casta/overridetree.cb D src/mainboard/google/octopus/variants/casta/variant.c D src/mainboard/google/octopus/variants/dood/Makefile.inc D src/mainboard/google/octopus/variants/dood/gpio.c D src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/dood/include/variant/ec.h D src/mainboard/google/octopus/variants/dood/include/variant/gpio.h D src/mainboard/google/octopus/variants/dood/overridetree.cb D src/mainboard/google/octopus/variants/dood/variant.c D src/mainboard/google/octopus/variants/fleex/Makefile.inc D src/mainboard/google/octopus/variants/fleex/gpio.c D src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/fleex/include/variant/ec.h D src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h D src/mainboard/google/octopus/variants/fleex/overridetree.cb D src/mainboard/google/octopus/variants/foob/Makefile.inc D src/mainboard/google/octopus/variants/foob/gpio.c D src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/foob/include/variant/ec.h D src/mainboard/google/octopus/variants/foob/include/variant/gpio.h D src/mainboard/google/octopus/variants/foob/overridetree.cb D src/mainboard/google/octopus/variants/foob/variant.c D src/mainboard/google/octopus/variants/garg/Makefile.inc D src/mainboard/google/octopus/variants/garg/gpio.c D src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/garg/include/variant/ec.h D src/mainboard/google/octopus/variants/garg/include/variant/gpio.h D src/mainboard/google/octopus/variants/garg/include/variant/sku.h D src/mainboard/google/octopus/variants/garg/overridetree.cb D src/mainboard/google/octopus/variants/garg/variant.c D src/mainboard/google/octopus/variants/lick/Makefile.inc D src/mainboard/google/octopus/variants/lick/gpio.c D src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/lick/include/variant/ec.h D src/mainboard/google/octopus/variants/lick/include/variant/gpio.h D src/mainboard/google/octopus/variants/lick/overridetree.cb D src/mainboard/google/octopus/variants/meep/Makefile.inc D src/mainboard/google/octopus/variants/meep/gpio.c D src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/meep/include/variant/ec.h D src/mainboard/google/octopus/variants/meep/include/variant/gpio.h D src/mainboard/google/octopus/variants/meep/include/variant/sku.h D src/mainboard/google/octopus/variants/meep/overridetree.cb D src/mainboard/google/octopus/variants/meep/variant.c D src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/octopus/include/variant/ec.h D src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h D src/mainboard/google/octopus/variants/phaser/Makefile.inc D src/mainboard/google/octopus/variants/phaser/gpio.c D src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/phaser/include/variant/ec.h D src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h D src/mainboard/google/octopus/variants/phaser/mainboard.c D src/mainboard/google/octopus/variants/phaser/overridetree.cb D src/mainboard/google/octopus/variants/phaser/variant.c D src/mainboard/google/octopus/variants/yorp/Makefile.inc D src/mainboard/google/octopus/variants/yorp/gpio.c D src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/yorp/include/variant/ec.h D src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h D src/mainboard/google/octopus/variants/yorp/overridetree.cb M src/mainboard/microtech/etabpro/Kconfig M src/mainboard/microtech/etabpro/Kconfig.name M src/mainboard/microtech/etabpro/Makefile.inc D src/mainboard/microtech/etabpro/boardid.c M src/mainboard/microtech/etabpro/bootblock.c D src/mainboard/microtech/etabpro/chromeos.c M src/mainboard/microtech/etabpro/dsdt.asl D src/mainboard/microtech/etabpro/ec.c D src/mainboard/microtech/etabpro/ec.h M src/mainboard/microtech/etabpro/gpio.c M src/mainboard/microtech/etabpro/mainboard.c M src/mainboard/microtech/etabpro/memory.c D src/mainboard/microtech/etabpro/nhlt.c M src/mainboard/microtech/etabpro/romstage.c D src/mainboard/microtech/etabpro/smihandler.c 123 files changed, 17 insertions(+), 6,973 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/39268/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39268 )
Change subject: Inicial device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39268/2/src/mainboard/microtech/eta... File src/mainboard/microtech/etabpro/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39268/2/src/mainboard/microtech/eta... PS2, Line 30: // mainboard_ec_init(); please, no space before tabs
Miroslaw Kocur has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39268 )
Change subject: Inicial device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard ......................................................................
Abandoned
mess
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build bot (Jenkins) (Code Review) -
Miroslaw Kocur (Code Review)