Change in coreboot[master]: soc/intel/skylake: Remove ABASE lock down programming

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21201

Change subject: soc/intel/skylake: Remove ABASE lock down programming
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soc/intel/skylake: Remove ABASE lock down programming

FSP is doing PMC ABASE lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove ABASE Lock down programming
from coreboot.

TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set.

Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/finalize.c
1 file changed, 1 insertion(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/21201/1

diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index a793e95..2fb37ca 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -126,12 +126,6 @@
    tcocnt |= TCO_LOCK;
    outw(tcocnt, tcobase + TCO1_CNT);

-	/* Lock down ABASE and sleep stretching policy */
-	dev = PCH_DEV_PMC;
-	reg32 = pci_read_config32(dev, GEN_PMCON_B);
-	reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
-	pci_write_config32(dev, GEN_PMCON_B, reg32);
-
    /* PMSYNC */
    pmcbase = pmc_mmio_regs();
    pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
@@ -141,7 +135,7 @@
    /* Display me status before we hide it */
    intel_me_status();

-	/* we should disable Heci1 based on the devicetree policy */
+	dev = PCH_DEV_PMC;
    config = dev->chip_info;

/*