[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU

[Wentao Qin (Code Review)]

Wentao Qin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84241?usp=email )

Change subject: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU
......................................................................

mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU

Check that lnkCap supports ASPM L1, so set it to ASPM_L1
to avoid excessive power consumption.

BUG=b:364484621, b:361828368
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

w/o this CL -
```
lotso-rev0 ~ # lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
    	LnkCap:	Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
    	LnkCtl:	ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+
```

w/ this CL -
```
lotso-rev0 ~ # lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
    	LnkCap:	Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
    	LnkCtl:	ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
```

Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6
Signed-off-by: Wentao Qin 
---
M src/mainboard/google/brox/variants/lotso/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/84241/1

diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index 85a3506..2970635 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -326,6 +326,7 @@
    			.clk_req = 0,
    			.clk_src = 0,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1,
    		}"
    		probe STORAGE STORAGE_NVME
    		probe unprovisioned