Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59195 )
Change subject: WIP soc: Added dram information to cbmem WIP ......................................................................
WIP soc: Added dram information to cbmem WIP
Signed-off-by: Ravi Kumar Bokka rbokka@codeaurora.org Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 --- M src/soc/qualcomm/common/include/soc/mmu_common.h M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7280/memlayout.ld 5 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59195/1
diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h index b6c8aab..38909fd 100644 --- a/src/soc/qualcomm/common/include/soc/mmu_common.h +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -11,6 +11,7 @@ #define DEV_MEM (MA_DEV | MA_S | MA_RW)
static struct region * const ddr_region = (struct region *)_ddr_information; +static struct region * const mem_chip_region = (struct region *)_mem_chip_info;
void soc_mmu_dram_config_post_dram_init(void); void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size); diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index c906ef2..1f2ff16 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -22,6 +22,7 @@ #define QCLIB_TE_DDR_TRAINING_DATA "ddr_training_data" #define QCLIB_TE_LIMITS_CFG_DATA "limits_cfg_data" #define QCLIB_TE_QCSDI "qcsdi" +#define QCLIB_TE_MEM_CHIP_INFO "mem_chip_info" /* memchip info */
/* BA_BMASK_VALUES (blob_attributes bit mask values) */ #define QCLIB_BA_SAVE_TO_STORAGE 0x00000001 diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index 7560266..7a7edfe 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -26,5 +26,6 @@ DECLARE_REGION(shrm) DECLARE_REGION(dram_cpucp) DECLARE_REGION(dram_modem) +DECLARE_REGION(mem_chip_info)
#endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index e016f25..3785505 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -18,6 +18,73 @@ #include <vb2_api.h>
#define QCLIB_VERSION 0 +#define TEST_CODE 1 + +static void write_mem_chip_information(struct qclib_cb_if_table_entry *te); +void *mem_chip_offset; +uint32_t mem_chip_size; + +#if TEST_CODE /* Added this structure for testing purpose, will be remove once changes are reviewd */ +#define DDR_MAX_NUM_CH_TEST 2 +typedef struct +{ + uint64_t type; // enum that differentiates DDR3, LPDDR3, LPDDR4, etc. + uint64_t num_channels; // To know how may channels are available. + uint64_t reserved[6]; // Reserved [6] + struct + { + uint64_t density; // Total density Seen on channel + uint64_t io_width; // JEDEC MR8 - io width + uint64_t manufacturer_id; // JEDEC MR5 + uint64_t revision_id[2]; // JEDEC MR6, MR7 + uint64_t reserved[4]; // Reserved + uint64_t serial_id[8]; // for potential future LPDDR5 expansion + } channels[DDR_MAX_NUM_CH_TEST]; +}dram_info; +#endif /* End of TEST_CODE */ + +static void write_mem_chip_information(struct qclib_cb_if_table_entry *te) +{ + /* Save MEM CHIP info in SRAM region to share with ramstage */ + mem_chip_offset = (void *)te->blob_address; + mem_chip_size = te->size; + +#if TEST_CODE /* Added this for testing purpose, will be remove once changes are reviewd */ + dram_info memchip; + /* Test Code to print memchip information before adding cbmem_add */ + printk(BIOS_INFO, "%s:%s: Test Code to print memchip information before adding cbmem_add\n", __FILE__, __func__); + memcpy(&memchip, (struct dram_info *)te->blob_address, sizeof(memchip)); + printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); + printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); + printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); + printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); +#endif /* End of TEST_CODE */ +} + +static void add_mem_chip_info(int unused) +{ + void *mem_region_base; + + /* Add cbmem */ + mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, mem_chip_size); + ASSERT(mem_region_base != NULL); + + /* Migrate the data into CBMEM */ + memcpy(mem_region_base, mem_chip_offset, mem_chip_size); + +#if TEST_CODE /* Added this for testing purpose, will be remove once changes are reviewd */ + dram_info memchip; + /* Test Code to print memchip information after adding cbmem_addd */ + printk(BIOS_INFO, "%s:%s: Test Code to print memchip information after adding cbmem_add\n", __FILE__, __func__); + memcpy(&memchip, (struct dram_info *)mem_region_base, sizeof(memchip)); + printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); + printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); + printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); + printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); +#endif /* End of TEST_CODE */ +} + +ROMSTAGE_CBMEM_INIT_HOOK(add_mem_chip_info);
struct qclib_cb_if_table qclib_cb_if_table = { .magic = QCLIB_MAGIC_NUMBER, @@ -86,6 +153,9 @@ sizeof(te->name))) {
write_qclib_log_to_cbmemc(te); + } else if (!strncmp(QCLIB_TE_MEM_CHIP_INFO, te->name, + sizeof(te->name))) { + write_mem_chip_information(te);
} else {
@@ -139,6 +209,10 @@ qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, _ddr_training, REGION_SIZE(ddr_training), 0);
+ /* Attempt to read MEM CHIP information */ + qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, + _mem_chip_info, REGION_SIZE(mem_chip_info), 0); + /* Attempt to load PMICCFG Blob */ data_size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", _pmic, REGION_SIZE(pmic)); diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 1677dc4..3a9c3b5 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -48,6 +48,7 @@ REGION(pmic, 0x14866000, 96K, 4K) REGION(ddr_training, 0x1487E000, 32K, 4K) REGION(qclib, 0x14886000, 800K, 4K) + REGION(mem_chip_info, 0x1494E000, 1K, 1K) /* memchip info */ BSRAM_END(0x14950000)
DRAM_START(0x80000000)