New patch to review for coreboot: 4b6aca4 util/inteltool: Add pci id mask to allow 4 northbridge models instead of 1.
Damien Zammit (damien@zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5873
-gerrit
commit 4b6aca44104d36ef7ea9693438db020577c845dc Author: Damien Zammit damien@zamaudio.com Date: Mon May 26 23:00:23 2014 +1000
util/inteltool: Add pci id mask to allow 4 northbridge models instead of 1.
This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core. Tested on 0x0150.
Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c Signed-off-by: Damien Zammit damien@zamaudio.com --- util/inteltool/inteltool.c | 2 +- util/inteltool/memory.c | 2 +- util/inteltool/pcie.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 219d84e..9d201b1 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -74,7 +74,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN & ~0xc, "3rd generation (Ivy Bridge family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 18382e5..a384cc0 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -251,7 +251,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: mch_registers = sandybridge_mch_registers; size = ARRAY_SIZE(sandybridge_mch_registers); - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */ + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN & ~0xc: /* pretty printing not implemented yet */ mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index cafd34a..cf02227 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -239,7 +239,7 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: dmi_registers = sandybridge_dmi_registers; size = ARRAY_SIZE(sandybridge_dmi_registers); - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */ + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN & ~0xc: /* pretty printing not implemented yet */ dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
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Damien Zammit