Change in coreboot[master]: spd/lp5: Generate initial SPDs for Sabrina SoC

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Karthik Ramasubramanian.
Hello build bot (Jenkins), Reka Norman, Reka Norman, Nick Vaccaro, Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/61543

to look at the new patch set (#3).

Change subject: spd/lp5: Generate initial SPDs for Sabrina SoC
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spd/lp5: Generate initial SPDs for Sabrina SoC

Mainboards using Sabrina SoC will be using LP5 memory technology.
Generate the initial set of SPDs for the existing LP5 memory parts.

BUG=b:211510456
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: Karthikeyan Ramasubramanian 
Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8
---
M spd/lp5/platforms_manifest.generated.txt
A spd/lp5/set-1/parts_spd_manifest.generated.txt
A spd/lp5/set-1/spd-1.hex
A spd/lp5/set-1/spd-2.hex
A spd/lp5/set-1/spd-3.hex
A spd/lp5/set-1/spd-empty.hex
6 files changed, 136 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/61543/3