Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79919?usp=email )
Change subject: soc/intel/jasperlake: Drop redundant PcieRpEnable ......................................................................
soc/intel/jasperlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead.
Note: Jenkins will fail because somebody has to go through all the dts.
Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/chip.c M src/soc/intel/jasperlake/chip.h A src/soc/intel/jasperlake/include/soc/pcie.h A src/soc/intel/jasperlake/pcie_rp.c M src/soc/intel/jasperlake/romstage/fsp_params.c 7 files changed, 27 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/79919/1
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 957ab1d..59d69dc 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -63,11 +63,6 @@ register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1"
- # PCIe port 1 for M.2 E-key WLAN - # Enable Root Port 4(x4) for NVMe - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable ClkReqDetect 1 for WLAN # Enable ClkReqDetect 4 for NVMe register "PcieRpClkReqDetect[1]" = "1" @@ -469,14 +464,8 @@
device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 on end # PCI Express Port 2 - WLAN - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.1 on end # PCI Express Port 2 - M.2 E-key WLAN device pci 1c.4 on end # PCI Express Port 5 - NVMe - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 31ea865..1377fff 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c +romstage-y += pcie_rp.c romstage-y += reset.c
ramstage-y += acpi.c @@ -35,6 +36,7 @@ ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += systemagent.c diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index c049163f..d96244b 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -14,14 +14,10 @@ #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h>
-static const struct pcie_rp_group pch_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 66ad223..af7ee54 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -146,7 +146,6 @@ bool PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */ - bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ diff --git a/src/soc/intel/jasperlake/include/soc/pcie.h b/src/soc/intel/jasperlake/include/soc/pcie.h new file mode 100644 index 0000000..17710cc --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pcie.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_JASPERLAKE_PCIE_H__ +#define __SOC_JASPERLAKE_PCIE_H__ + +#include <intelblocks/pcie_rp.h> + +extern const struct pcie_rp_group pch_rp_groups[]; + +#endif /* __SOC_JASPERLAKE_PCIE_H__ */ diff --git a/src/soc/intel/jasperlake/pcie_rp.c b/src/soc/intel/jasperlake/pcie_rp.c new file mode 100644 index 0000000..844cc54 --- /dev/null +++ b/src/soc/intel/jasperlake/pcie_rp.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> + +const struct pcie_rp_group pch_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { 0 } +}; diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 43a8c70..0132906 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -5,8 +5,10 @@ #include <device/device.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/romstage.h> #include <soc/soc_chip.h>
@@ -14,7 +16,6 @@ const struct soc_intel_jasperlake_config *config) { unsigned int i; - uint32_t mask = 0;
/* * If IGD is enabled, set IGD stolen size to 60MB. @@ -61,13 +62,7 @@ } }
- /* PCIe root port configuration */ - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - - m_cfg->PcieRpEnableMask = mask; + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(pch_rp_groups);
FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage); FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq);
-
Nico Huber (Code Review)