[XS] Change in coreboot[master]: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"

[Subrata Banik (Code Review)]

Attention is currently required from: John Zhao, Kapil Porwal, Tarun Tuli, Tim Wawrzynczak, Utkarsh H Patel.

Hello build bot (Jenkins), Utkarsh H Patel, Tarun Tuli, John Zhao, Tim Wawrzynczak, Kapil Porwal,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/84367?usp=email

to review the following change.

Change subject: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"
......................................................................

Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"

This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309.

This workaround is not valid with the latest Intel PRQ silicon,
so I'm dropping it now. I was able to boot to ChromeOS without any
hang, and I also ran an S0ix cycle without any failures.

BUG=b:244082753
TEST=Able to boot google/rex0 to CrOS.

Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
---
M src/soc/intel/meteorlake/acpi/tcss.asl
1 file changed, 1 insertion(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/84367/1

diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl
index c2212f0..87d6521 100644
--- a/src/soc/intel/meteorlake/acpi/tcss.asl
+++ b/src/soc/intel/meteorlake/acpi/tcss.asl
@@ -719,13 +719,7 @@
    	}

/* Request IOM for D3 cold entry sequence. */
-		/*
-		 * FIXME: Remove this workaround after resolving b/244082753
-		 *
-		 * Document #742990: TCCold exit flow may not complete when processor at package
-		 * C0. The implication is that the system may hang.
-		 */
-		// TD3C = 1
+		TD3C = 1
    }

PowerResource (D3C, 5, 0)