Lee Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15865
-gerrit
commit fe6ce6ac5701b368a1da7378d31c9036d28ed718 Author: Lee Leahy leroy.p.leahy@intel.com Date: Mon Jul 25 07:41:54 2016 -0700
soc/intel/quark: Add FSP 2.0 boot block support
Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build.
TEST=Bulid and run bootblock on Galileo Gen2
Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/mainboard/intel/galileo/Kconfig | 1 + src/mainboard/intel/galileo/Makefile.inc | 3 +++ src/mainboard/intel/galileo/gpio.c | 4 ++++ src/mainboard/intel/galileo/romstage.c | 2 ++ src/soc/intel/quark/Makefile.inc | 10 +++++++++ src/soc/intel/quark/fsp2_0.c | 26 +++++++++++++++++++++ src/soc/intel/quark/include/soc/car.h | 29 ++++++++++++++++++++++++ src/soc/intel/quark/include/soc/ramstage.h | 6 +++++ src/soc/intel/quark/include/soc/romstage.h | 4 ++++ src/soc/intel/quark/memmap.c | 4 +++- src/soc/intel/quark/reset.c | 31 ++++++++++++++++++++++++++ src/soc/intel/quark/romstage/Makefile.inc | 3 +++ src/soc/intel/quark/romstage/car_stage_entry.S | 2 ++ src/soc/intel/quark/romstage/fsp2_0.c | 26 +++++++++++++++++++++ 14 files changed, 150 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index d06b0ba..f043474 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -55,6 +55,7 @@ config USE_FSP1_1 config USE_FSP2_0 bool default n + select HAVE_HARD_RESET select PLATFORM_USES_FSP2_0 select POSTCAR_STAGE
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 5aad308..efaf007 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -23,5 +23,8 @@ bootblock-y += reg_access.c romstage-y += gpio.c romstage-y += reg_access.c
+postcar-y += gpio.c +postcar-y += reg_access.c + ramstage-y += gpio.c ramstage-y += reg_access.c diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index 8f3c2e3..f654d19 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -15,7 +15,11 @@
#include <arch/io.h> #include <console/console.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> +#else +#include <soc/car.h> +#endif #include <soc/ramstage.h> #include "reg_access.h" #include "gen1.h" diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c index dfae772..baf9af3 100644 --- a/src/mainboard/intel/galileo/romstage.c +++ b/src/mainboard/intel/galileo/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h>
/* All FSP specific code goes in this block */ @@ -22,3 +23,4 @@ void mainboard_romstage_entry(struct romstage_params *rp) /* Call back into chipset code with platform values updated. */ romstage_common(rp); } +#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */ diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 4740ec7..52d77bf 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -31,22 +31,32 @@ romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
+postcar-y += fsp2_0.c +postcar-y += i2c.c +postcar-y += memmap.c +postcar-y += reg_access.c +postcar-y += tsc_freq.c +postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += reg_access.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include +CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp
# Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c new file mode 100644 index 0000000..126e131 --- /dev/null +++ b/src/soc/intel/quark/fsp2_0.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <fsp/util.h> +#include <soc/ramstage.h> + +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +{ +} + +asmlinkage void chipset_teardown_car(void) +{ + console_init(); +} diff --git a/src/soc/intel/quark/include/soc/car.h b/src/soc/intel/quark/include/soc/car.h new file mode 100644 index 0000000..23c6a24 --- /dev/null +++ b/src/soc/intel/quark/include/soc/car.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CAR_H_ +#define _SOC_CAR_H_ + +#include <fsp/util.h> + +/* Mainboard and SoC initialization prior to console. */ +void car_mainboard_pre_console_init(void); +void car_soc_pre_console_init(void); + +/* Mainboard and SoC initialization post console initialization. */ +void car_mainboard_post_console_init(void); +void car_soc_post_console_init(void); + +#endif /* _SOC_CAR_H_ */ diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 9f201a0..b5e15ae 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -19,10 +19,16 @@
#include <chip.h> #include <device/device.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/ramstage.h> +#endif #include <soc/QuarkNcSocId.h>
void mainboard_gpio_i2c_init(device_t dev); +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) void fsp_silicon_init(void); +#else +asmlinkage void chipset_teardown_car(void); +#endif
#endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index fcac3e2..d6f9186 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,7 +22,11 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> +#else +#include <soc/car.h> +#endif #include <soc/reg_access.h>
asmlinkage void *car_stage_c_entry(void); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index f880443..28f8852 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -14,15 +14,17 @@ */
#include <cbmem.h> +#include <soc/reg_access.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/memmap.h> #include <soc/QuarkNcSocId.h> -#include <soc/reg_access.h>
size_t mmap_region_granularity(void) { /* Align to 8 MiB by default */ return 8 << 20; } +#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */
void *cbmem_top(void) { diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c new file mode 100644 index 0000000..e898432 --- /dev/null +++ b/src/soc/intel/quark/reset.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <reset.h> + +void chipset_handle_reset(enum fsp_status status) +{ + switch(status) { + case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ + hard_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 635da83..329138b 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,7 +16,10 @@ romstage-y += car.c romstage-y += car_stage_entry.S romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c + +postcar-y += mtrr.c diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index d0a0db0..b820711 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,9 +29,11 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #if !ENV_VERSTAGE #include "src/drivers/intel/fsp1_1/after_raminit.S" #endif +#endif
/* The code should never reach this point */ movb $0x69, %ah diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c new file mode 100644 index 0000000..494f84a --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/romstage.h> + +asmlinkage void *car_stage_c_entry(void) +{ + post_code(0x20); + console_init(); + return NULL; +}
-
Lee Leahy