Change in coreboot[master]: soc/intel/alderlake: Send EOP over multithreaded environment

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63028 )

Change subject: soc/intel/alderlake: Send EOP over multithreaded environment
......................................................................

soc/intel/alderlake: Send EOP over multithreaded environment

This patch sends CSE EOP command using non-BSP core.

TEST=Able to see CSE EOP command is successful.

Signed-off-by: Subrata Banik 
Change-Id: Iabe4a56d7f52b0cd7133acd8c434cd3ee1bd9297
---
M src/soc/intel/alderlake/chip.c
1 file changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/63028/1

diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 699b39d..91ce8a3 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -2,6 +2,7 @@

#include <device/device.h>
 #include <device/pci.h>
+#include <cpu/x86/mp.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
 #include <intelblocks/acpi.h>
@@ -18,6 +19,8 @@
 #include <soc/pcie.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
+#include <smp/node.h>
+#include <timer.h>

#if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
@@ -134,6 +137,11 @@
    gpio_pm_configure(value, TOTAL_GPIO_COMM);
 }

+static void send_eop_on_non_bsp(void *unused)
+{
+	cse_send_end_of_post();
+}
+
 void soc_init_pre_device(void *chip_info)
 {
    /* Perform silicon specific init. */
@@ -161,7 +169,7 @@
     */
    if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY)) {
    	printk(BIOS_INFO, "Sending EOP early from SoC\n");
-		cse_send_end_of_post();
+		mp_run_on_aps(&send_eop_on_non_bsp, NULL, boot_cpu() + 1, 1000 * USECS_PER_MSEC);
    }
 }