Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the amd firmware ......................................................................
soc/amd/picasso: Use cbfs to locate the amd firmware
Switch from hardcoded locations for the AMD firmware in the RW_A & RW_B regions to locating it with cbfs.
BUG=b:154441227 TEST=None yet
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h 4 files changed, 41 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42831/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d07af6..a2321e5 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -520,16 +520,6 @@ Add a space-delimited list of filenames that should only be in the RW-B section.
-config PICASSO_FW_A_POSITION - hex - help - Location of the AMD firmware in the RW_A region - -config PICASSO_FW_B_POSITION - hex - help - Location of the AMD firmware in the RW_B region - endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 35bc1e7..29d1c42 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -497,12 +497,10 @@ ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_A_POSITION)) apu/amdfw_a-type := raw
cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_B_POSITION)) apu/amdfw_b-type := raw endif
diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index de41e4c..4470c63 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -4,7 +4,10 @@
#include <bl_uapp/bl_syscall_public.h> #include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> #include <console/console.h> +#include <fmap.h> #include <security/vboot/misc.h> #include <security/vboot/symbols.h> #include <security/vboot/vboot_common.h> @@ -33,6 +36,21 @@ vboot_reboot(); }
+static uintptr_t locate_amdfw(const char *name, struct region_device *rdev) +{ + uint32_t cbfs_type = CBFS_TYPE_RAW; + struct cbfsf fh; + + if (!region_device_sz(&(fh.data))) { + if (cbfs_locate_file_in_region(&fh, "COREBOOT", name, &cbfs_type)) { + printk(BIOS_ERR, "Error: AMD Firmware table could not be found.\n"); + return 0; + } + } + + return (uintptr_t)rdev_mmap_full(&fh.data); +} + /* * Tell the PSP where to load the rest of the firmware from */ @@ -41,6 +59,9 @@ struct psp_ef_table *ef_table; uint32_t psp_dir_addr, bios_dir_addr; uint32_t *psp_dir_in_spi, *bios_dir_in_spi; + const char *rname, *fname; + struct region_device rdev; + uintptr_t amdfw_location;
/* Continue booting from RO */ if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) { @@ -49,14 +70,26 @@ }
if (vboot_is_firmware_slot_a(ctx)) { - printk(BIOS_SPEW, "Using FMAP RW_A region.\n"); - ef_table = (struct psp_ef_table *)((CONFIG_PICASSO_FW_A_POSITION & - SPI_ADDR_MASK) + (uint32_t)boot_dev.base); + rname = "FW_MAIN_A"; + fname = "apu/amdfw_a"; } else { - printk(BIOS_SPEW, "Using FMAP RW_B region.\n"); - ef_table = (struct psp_ef_table *)((CONFIG_PICASSO_FW_B_POSITION & - SPI_ADDR_MASK) + (uint32_t)boot_dev.base); + rname = "FW_MAIN_B"; + fname = "apu/amdfw_a"; } + printk(BIOS_DEBUG, "Using FMAP %s region.\n", rname); + + if (fmap_locate_area_as_rdev(rname, &rdev)){ + printk(BIOS_ERR, "Error: Could not locate fmap region %s.\n", rname); + return POSTCODE_FMAP_REGION_MISSING; + } + + amdfw_location = locate_amdfw(fname, &rdev); + if (!amdfw_location) { + printk(BIOS_ERR, "Error: AMD Firmware table not found.\n"); + return POSTCODE_AMD_FW_MISSING; + } + ef_table = (struct psp_ef_table *)((amdfw_location & SPI_ADDR_MASK) + + (uint32_t)boot_dev.base);
if (ef_table->signature != EMBEDDED_FW_SIGNATURE) { printk(BIOS_ERR, "Error: ROMSIG address is not correct.\n"); diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.h b/src/soc/amd/picasso/psp_verstage/psp_verstage.h index 6fe5c7a..2b1105a 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.h +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.h @@ -28,6 +28,8 @@ #define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5 #define POSTCODE_BDT1_COOKIE_MISMATCH_ERROR 0xC6 #define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7 +#define POSTCODE_FMAP_REGION_MISSING 0xC8 +#define POSTCODE_AMD_FW_MISSING 0xc9
#define POSTCODE_UNMAP_SPI_ROM 0xF0 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 2:
This change is ready for review.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 44: if (cbfs_locate(&fh, rdev, name, &type)) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 78: if (fmap_locate_area_as_rdev(rname, &rdev)){ space required before the open brace '{'
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.h:
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 32: #define POSTCODE_AMD_FW_MISSING 0xc9 inconsistent capitalization
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 89: (uint32_t)boot_dev.base); I believe you want an absolute address from the spi mapping, correct? The address returned from locate_amdfw() already is based off boot_dev because the fmap_locate_area_as_rdev() uses the boot device.
Hello build bot (Jenkins), Raul Rangel, Patrick Georgi, Eric Peers, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42831
to look at the new patch set (#3).
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
soc/amd/picasso: Use cbfs to locate the AMD firmware
Switch from locating the AMD firmware in the RW_A & RW_B regions by their hardcoded locations to using CBFS to find them. They still need to be at the hardcoded locations so that we can set the location address inside the binary, but instead of just setting the pointer directly to them, we now search for them with cbfs.
BUG=b:154441227 TEST=Boot & verify that binaries are located in both RW-A & RW-B
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002 --- M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h 2 files changed, 37 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42831/3
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.h:
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 32: #define POSTCODE_AMD_FW_MISSING 0xc9
inconsistent capitalization
Done
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 89: (uint32_t)boot_dev.base);
I believe you want an absolute address from the spi mapping, correct? The address returned from loc […]
Right. Updated the code here and below to remove the adjustments that are no longer needed.
Hello build bot (Jenkins), Raul Rangel, Patrick Georgi, Eric Peers, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42831
to look at the new patch set (#4).
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
soc/amd/picasso: Use cbfs to locate the AMD firmware
Switch from locating the AMD firmware in the RW_A & RW_B regions with their hardcoded locations to using CBFS to find them. They still need to be at the hardcoded locations so that we can set the location inside the binary, but instead of just setting the pointer directly to them, we now search for them with cbfs.
BUG=b:154441227 TEST=Boot & verify that binaries are located in both RW-A & RW-B
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002 --- M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h 2 files changed, 38 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42831/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42831/4/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/4/src/soc/amd/picasso/psp_ver... PS4, Line 44: if (cbfs_locate(&fh, rdev, name, &type)) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/42831/4/src/soc/amd/picasso/psp_ver... PS4, Line 78: if (fmap_locate_area_as_rdev(rname, &rdev)){ space required before the open brace '{'
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 4: Code-Review+2
Hello build bot (Jenkins), Raul Rangel, Patrick Georgi, Eric Peers, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42831
to look at the new patch set (#5).
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
soc/amd/picasso: Use cbfs to locate the AMD firmware
Switch from locating the AMD firmware in the RW_A & RW_B regions with their hardcoded locations to using CBFS to find them. They still need to be at the hardcoded locations so that we can set the location inside the binary, but instead of just setting the pointer directly to them, we now search for them with cbfs.
BUG=b:154441227 TEST=Boot & verify that binaries are located in both RW-A & RW-B
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002 --- M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h 2 files changed, 38 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42831/5
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 5: Code-Review+2
Hello build bot (Jenkins), Raul Rangel, Patrick Georgi, Eric Peers, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42831
to look at the new patch set (#6).
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
soc/amd/picasso: Use cbfs to locate the AMD firmware
Switch from locating the AMD firmware in the RW_A & RW_B regions with their hardcoded locations to using CBFS to find them. They still need to be at the hardcoded locations so that we can set the location inside the binary, but instead of just setting the pointer directly to them, we now search for them with cbfs.
BUG=b:154441227 TEST=Boot & verify that binaries are located in both RW-A & RW-B
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002 --- M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h 2 files changed, 36 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42831/6
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 89: (uint32_t)boot_dev.base);
Right. Updated the code here and below to remove the adjustments that are no longer needed.
The code below is still needed. We get the psp_dir_addr & bios_dir_addr out of the table, and those are not based off of boot_dev.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 89: (uint32_t)boot_dev.base);
The code below is still needed. […]
Martin, can you please elaborate on that? What addresses are you getting that are different? I'm not following your comment.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 89: (uint32_t)boot_dev.base);
Martin, can you please elaborate on that? What addresses are you getting that are different? I'm not […]
Nevermind. I see now. Are the values of psp_table and bios1_entry pointers in memory-mapped x86 view of things? Or are they offests in SPI flash address space?
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/2/src/soc/amd/picasso/psp_ver... PS2, Line 89: (uint32_t)boot_dev.base);
Nevermind. I see now. […]
They're direct memory mapped addresses in the x86 address space.
Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 6: Code-Review+1
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 6: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/42831/6/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/6/src/soc/amd/picasso/psp_ver... PS6, Line 94: psp_dir_addr = ef_table->psp_table; I think a comment here would go a long way for indicating the point of the math below.
https://review.coreboot.org/c/coreboot/+/42831/6/src/soc/amd/picasso/psp_ver... PS6, Line 98: bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + Not for this patch, but we really should have used the offsets calculated w/ SPI_ADDR_MASK.
static void *x86_spi_addrspace_to_psp(uintptr_t base, size_t size) { const struct region_device *bootdev = boot_device_ro();
return rdev_mmap(bootdev, base & SPI_ADDR_MASK, size); }
That would perform all the necessary math for the magic field sanity check.
That or just rdev_readat():
static bool x86_spi_addrspace_magic_check(uintptr_t base, uint32_t match) { const struct region_device *bootdev = boot_device_ro(); uint32_t value.
if (rdev_readat(bootdev, &value, base & SPI_ADDR_MASK, sizeof(match)) != sizeof(match) { // fail return false; } return value == match; }
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/42831/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42831/7//COMMIT_MSG@12 PS7, Line 12: the binary Which binary requires the hard coding? Is it possible to also remove this hard coding?
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42831/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42831/7//COMMIT_MSG@12 PS7, Line 12: the binary
Which binary requires the hard coding? Is it possible to also remove this hard coding?
The AMD firmware table requires the addresses. The initial pointer for the bootloader is interpreted at least in part by hardware (or built in code), so I don't think it's possible to change this easily.
https://review.coreboot.org/c/coreboot/+/42831/6/src/soc/amd/picasso/psp_ver... File src/soc/amd/picasso/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/42831/6/src/soc/amd/picasso/psp_ver... PS6, Line 94: psp_dir_addr = ef_table->psp_table;
I think a comment here would go a long way for indicating the point of the math below.
I'm refactoring this section in follow-on patch. Also, I believe that Zheng Bao may be refactoring this tool as well, but I'm not sure what he's doing other than replacing the command line arguments with a config file instead.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42831 )
Change subject: soc/amd/picasso: Use cbfs to locate the AMD firmware ......................................................................
soc/amd/picasso: Use cbfs to locate the AMD firmware
Switch from locating the AMD firmware in the RW_A & RW_B regions with their hardcoded locations to using CBFS to find them. They still need to be at the hardcoded locations so that we can set the location inside the binary, but instead of just setting the pointer directly to them, we now search for them with cbfs.
BUG=b:154441227 TEST=Boot & verify that binaries are located in both RW-A & RW-B
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42831 Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Eric Peers epeers@google.com Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h 2 files changed, 36 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Raul Rangel: Looks good to me, approved Eric Peers: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index bea0688..2524651 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -4,7 +4,10 @@
#include <bl_uapp/bl_syscall_public.h> #include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> #include <console/console.h> +#include <fmap.h> #include <security/vboot/misc.h> #include <security/vboot/symbols.h> #include <security/vboot/vboot_common.h> @@ -31,6 +34,19 @@ vboot_reboot(); }
+static uintptr_t locate_amdfw(const char *name, struct region_device *rdev) +{ + struct cbfsf fh; + uint32_t type = CBFS_TYPE_RAW; + + if (cbfs_locate(&fh, rdev, name, &type)) + return 0; + + cbfs_file_data(rdev, &fh); + + return (uintptr_t)rdev_mmap_full(rdev); +} + /* * Tell the PSP where to load the rest of the firmware from */ @@ -39,6 +55,9 @@ struct psp_ef_table *ef_table; uint32_t psp_dir_addr, bios_dir_addr; uint32_t *psp_dir_in_spi, *bios_dir_in_spi; + const char *rname, *fname; + struct region_device rdev; + uintptr_t amdfw_location;
/* Continue booting from RO */ if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) { @@ -47,15 +66,24 @@ }
if (vboot_is_firmware_slot_a(ctx)) { - printk(BIOS_SPEW, "Using FMAP RW_A region.\n"); - ef_table = (struct psp_ef_table *)((CONFIG_PICASSO_FW_A_POSITION & - SPI_ADDR_MASK) + (uint32_t)boot_dev.base); + rname = "FW_MAIN_A"; + fname = "apu/amdfw_a"; } else { - printk(BIOS_SPEW, "Using FMAP RW_B region.\n"); - ef_table = (struct psp_ef_table *)((CONFIG_PICASSO_FW_B_POSITION & - SPI_ADDR_MASK) + (uint32_t)boot_dev.base); + rname = "FW_MAIN_B"; + fname = "apu/amdfw_b"; }
+ if (fmap_locate_area_as_rdev(rname, &rdev)) { + printk(BIOS_ERR, "Error: Could not locate fmap region %s.\n", rname); + return POSTCODE_FMAP_REGION_MISSING; + } + + amdfw_location = locate_amdfw(fname, &rdev); + if (!amdfw_location) { + printk(BIOS_ERR, "Error: AMD Firmware table not found.\n"); + return POSTCODE_AMD_FW_MISSING; + } + ef_table = (struct psp_ef_table *)amdfw_location; if (ef_table->signature != EMBEDDED_FW_SIGNATURE) { printk(BIOS_ERR, "Error: ROMSIG address is not correct.\n"); return POSTCODE_ROMSIG_MISMATCH_ERROR; diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.h b/src/soc/amd/picasso/psp_verstage/psp_verstage.h index e7d6daf..ad422fc 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.h +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.h @@ -28,6 +28,8 @@ #define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5 #define POSTCODE_BDT1_COOKIE_MISMATCH_ERROR 0xC6 #define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7 +#define POSTCODE_FMAP_REGION_MISSING 0xC8 +#define POSTCODE_AMD_FW_MISSING 0xC9
#define POSTCODE_UNMAP_SPI_ROM 0xF0 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1
-
Aaron Durbin (Code Review) -
build bot (Jenkins) (Code Review)
-
Eric Peers (Code Review)
-
Martin Roth (Code Review)
-
Patrick Georgi (Code Review)
-
Raul Rangel (Code Review)