[S] Change in coreboot[main]: soc/intel/cannonlake: Set correct default sizes of Intel TXT memory

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83734?usp=email )

Change subject: soc/intel/cannonlake: Set correct default sizes of Intel TXT memory
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soc/intel/cannonlake: Set correct default sizes of Intel TXT memory

The CoffeeLake/CometLake requires the SINIT to be 320KB and the heap
of 960KB. The DPR should also be 4MB for these platforms. If these
regions are too small, the SINIT complains with error class 5 major
code 2 - insufficient HEAP size.

TEST=Boot Linux with tboot on Protectli VP4670 with TXT enabled.

Change-Id: I5340165579174eb8ab26dfaae452896d6646c900
Signed-off-by: Michał Żygowski 
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 13 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/83734/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index cc04929..7976466 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -336,10 +336,22 @@
    hex
    default 0xe00

+if INTEL_TXT
+
 config INTEL_TXT_BIOSACM_ALIGNMENT
-	hex
    default 0x40000 # 256KB

+config INTEL_TXT_DPR_SIZE
+	default 4 # 4MB
+
+config INTEL_TXT_SINIT_SIZE
+	default 0x50000 # 320KB
+
+config INTEL_TXT_HEAP_SIZE
+	default 0xf0000 # 960KB
+
+endif
+
 # To get all CPU features programmed properly for Intel TXT we need
 # to use FSP MP Init. Have not yet found a way to program the features
 # correctly and not have the FSP lock the registers before coreboot