[M] Change in coreboot[main]: soc/mediatek/mt8196: Add disable modem power driver

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin.

Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85651?usp=email )

Change subject: soc/mediatek/mt8196: Add disable modem power driver
......................................................................

Patch Set 3:

(8 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/85651/comment/8d550187_c1a2f334?usp... :
PS3, Line 7: disable modem power driver
modem power driver to disable unused power

File src/soc/mediatek/mt8196/include/soc/md_power_ctrl.h:

https://review.coreboot.org/c/coreboot/+/85651/comment/715ad173_8daad33e?usp... :
PS3, Line 6: /*
           :  * md_power_down() - Power down modem
           :  */
`/* Power down modem. */`

https://review.coreboot.org/c/coreboot/+/85651/comment/7849b714_22a9c652?usp... :
PS3, Line 9: md
> modem

Also rename the file to modem_power_ctrl.*.

File src/soc/mediatek/mt8196/md_power_ctrl.c:

https://review.coreboot.org/c/coreboot/+/85651/comment/1d579c43_ba13bfc2?usp... :
PS3, Line 28: mtk_apifrbus_ao_io_reg_bus
As this is used only in this file, can we have a shorter name?

https://review.coreboot.org/c/coreboot/+/85651/comment/3984858b_1fe0e54a?usp... :
PS3, Line 31: struct mtk_spm_regs {
            : 	u32 reserved0[896];
            : 	u32 md1_pwr_con;
            : 	u32 reserved1[20];
            : 	u32 adsp_top_pwr_con;
            : 	u32 adsp_infra_pwr_con;
            : 	u32 adsp_ao_pwr_con;
            : 	u32 reserved2[11];
            : 	u32 spu_hwrot_pwr_con;
            : 	u32 reserved3[27];
            : 	u32 md_buck_iso_con;
            : 	u32 reserved4[5];
            : 	u32 pwr_status;
            : 	u32 pwr_status_2nd;
            : };
            : 
            : static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
This is already defined in spm.h. Please rebase onto CB:85599.

https://review.coreboot.org/c/coreboot/+/85651/comment/74ed6362_e3c301dd?usp... :
PS3, Line 50: OTHER_SRAM_CKISO        = BIT(0),
            : 	PWR_RST_B		= BIT(0),
Are these both for the `md1_pwr_con` register?

https://review.coreboot.org/c/coreboot/+/85651/comment/2c8a9a89_030cd488?usp... :
PS3, Line 52: OTHER_SRAM_ISOINT_B	= BIT(1),
            : 	PWR_ISO			= BIT(1),
Same here. Why do we have two definitions for the same bit?

https://review.coreboot.org/c/coreboot/+/85651/comment/814c3d5d_da2b69a5?usp... :
PS3, Line 90: 	struct pmif *pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1);
            : 
            : 	/* Vsram_vosel = 0x24d, read Vsram value */
            : 	reg = VSRAM_VOSEL;
            : 	pmif_arb->read(pmif_arb, SPMI_SLAVE_4, reg, &val);
            : 
            : 	/* Vmodem_vosel = 0x24e, write Vmodem 0.75V */
            : 	reg = VMODEM_VOSEL;
            : 	pmif_arb->write(pmif_arb, SPMI_SLAVE_4, reg, SPMI_SLAVE_4_750MV);
            : 	pmif_arb->read(pmif_arb, SPMI_SLAVE_4, reg, &val);
> Add `mt6363_write8` to `common/mt6363.c`. […]

One minor side effect is that `pmif_check_init_done` will be called multiple times. As future improvement, we may store `bool is_init_done` in `struct pmif` to prevent multiple calls.