Attention is currently required from: Christian Walter, Jonathon Hall, Michael Niewöhner, Patrick Rudolph, Tarun Tuli.
Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76027?usp=email )
Change subject: mb/{cfl,cml,whl}: Use true/false macros for satapwroptimize dt option ......................................................................
mb/{cfl,cml,whl}: Use true/false macros for satapwroptimize dt option
The true/false macros give the reader a better understanding about how the option should be used. Thus, replace 0/1 with false/true.
While on it, remove the quotes from the option name and from the value.
Coffeelake, Cometlake and Whiskeylake mainboards which use that option were changed by the following command ran from the top level directory.
dt_line="chip soc/intel/cannonlake" && \ option="satapwroptimize" && \ grep -r "${dt_line}" src/mainboard | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/"${option}".*=.*"1"/${option} = true/g" -e "s/"${option}".*=.*"0"/${option} = false/g"
Change-Id: I9416ea63ed8bd13f8fbf669b3f5bb5da1b9b1c73 Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb 8 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/76027/1
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 8e09cac..3d02e96 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -33,7 +33,7 @@ # Misc register AcousticNoiseMitigation = true #register "dmipwroptimize" = "1" - #register "satapwroptimize" = "1" + #register satapwroptimize = true
# Power register "PchPmSlpS3MinAssert" = "3" # 50ms diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2cf7598..f647e7e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -24,7 +24,7 @@ register "SataPortsDevSlp[1]" = "1" # Configure devslp pad reset to PLT_RST register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset" - register "satapwroptimize" = "1" + register satapwroptimize = true # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable S0ix diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index ae2d6a4..2672909 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -24,7 +24,7 @@ register "SataPortsDevSlp[1]" = "1" # Configure devslp pad reset to PLT_RST register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset" - register "satapwroptimize" = "1" + register satapwroptimize = true # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable S0ix diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4bb7815..52a9c4a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -29,7 +29,7 @@
register s0ix_enable = true register dptf_enable = true - register "satapwroptimize" = "1" + register satapwroptimize = true register "power_limits_config" = "{ .tdp_pl1_override = 25, .tdp_pl2_override = 51, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index a1fccfd..32220d3 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -32,7 +32,7 @@
register s0ix_enable = true register dptf_enable = true - register "satapwroptimize" = "1" + register satapwroptimize = true register AcousticNoiseMitigation = true register "SlowSlewRateForIa" = "2" register "SlowSlewRateForGt" = "2" diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index cdf22a8..b3fb66c 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -2,7 +2,7 @@ # FSP configuration
register SataSalpSupport = false - register "satapwroptimize" = "1" + register satapwroptimize = true register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1
register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb index e078827..350a444 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -143,7 +143,7 @@ end end device pci 17.0 on # SATA - register "satapwroptimize" = "1" + register satapwroptimize = true register SataSalpSupport = true # Port 2 (M.2 / inner) register "SataPortsEnable[1]" = "1" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb index cab254a..5725c25 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -126,7 +126,7 @@ device pci 17.0 on # SATA register "SataPortsEnable[0]" = "1" # 2.5" register "SataPortsEnable[2]" = "1" # m.2 - register "satapwroptimize" = "1" + register satapwroptimize = true end device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN) register "PcieRpSlotImplemented[7]" = "1"