Change in coreboot[master]: mb/google/brya/var/redrix: disabled autonomous GPIO power management

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59541 )

Change subject: mb/google/brya/var/redrix: disabled autonomous GPIO power management
......................................................................

mb/google/brya/var/redrix: disabled autonomous GPIO power management

Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:200918380
TEST=USE="project_redrix emerge-brya coreboot" and verify it builds
without error.

Change-Id: Ic43345e477c4e434947f3e74feb7b8e37df548cd
Signed-off-by: MAULIK V VAGHELA 
---
M src/mainboard/google/brya/variants/redrix/overridetree.cb
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/59541/1

diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index e4119f6..c1581b0 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -33,6 +33,17 @@
 chip soc/intel/alderlake
    register "SaGv" = "SaGv_Enabled"

+	# This disabled autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
    register "CnviBtAudioOffload" = "true"
    # FIVR RFI Spread Spectrum 6%
    register "FivrSpreadSpectrum" = "FIVR_SS_6"