[XS] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting

[David Wu (Code Review)]

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85519?usp=email )

Change subject: soc/intel/alderlake: Add support for PCIe speed setting
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soc/intel/alderlake: Add support for PCIe speed setting

This change provides config for devicetree to control PCIe speed

BUG=b:374205496
TEST=build pass

Change-Id: I32a9918a51faa903927a9646605a618744b527c0
Signed-off-by: David Wu 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85519/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index d4cbf0f..9672dcb 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1018,6 +1018,7 @@
    		s_cfg->PcieRpSlotImplemented[i] = 0;
    	s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
    	configure_pch_rp_power_management(s_cfg, rp_cfg, i);
+		s_cfg->PcieRpPcieSpeed[i] = rp_cfg->pcie_rp_pcie_speed;
    }
    s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);

diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 7f7dba6..dd9c0a0 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -71,6 +71,8 @@
    enum ASPM_control pcie_rp_aspm;
    /* timeout for device detect */
    uint32_t pcie_rp_detect_timeout_ms;
+	/* PCIE RP Pcie Speed. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 */
+	uint8_t pcie_rp_pcie_speed;
 };

/*