Change in coreboot[master]: [TESTME] nb/intel/x4x: Correct DDR3 turnaround table

[Angel Pons (Code Review)]

Attention is currently required from: Damien Zammit, Patrick Rudolph.
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49388 )

Change subject: [TESTME] nb/intel/x4x: Correct DDR3 turnaround table
......................................................................

[TESTME] nb/intel/x4x: Correct DDR3 turnaround table

Comparing against MRC, looks like the values for TA3 and TA4 are
backwards. All of them. Thus, correct the tables accordingly.

Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/x4x/raminit_ddr23.c
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/49388/1

diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 35d1c9f..e0e1a25 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -424,22 +424,22 @@

static const u8 ddr3_turnaround_tab[3][6][4] = {
    	{ /* DDR3 800 */
-			{0x9, 0x7, 0x7, 0x9},	/* CL = 5 */
+			{0x9, 0x7, 0x9, 0x7},	/* CL = 5 */
    		{0x9, 0x7, 0x8, 0x8},	/* CL = 6 */
    	},
    	{ /* DDR3 1066 */
    		{0x0, 0x0, 0x0, 0x0},	/* CL = 5 - Not supported */
-			{0x9, 0x7, 0x7, 0x9},	/* CL = 6 */
+			{0x9, 0x7, 0x9, 0x7},	/* CL = 6 */
    		{0x9, 0x7, 0x8, 0x8},	/* CL = 7 */
-			{0x9, 0x7, 0x9, 0x7}	/* CL = 8 */
+			{0x9, 0x7, 0x7, 0x9}	/* CL = 8 */
    	},
    	{ /* DDR3 1333 */
    		{0x0, 0x0, 0x0, 0x0},	/* CL = 5 - Not supported */
    		{0x0, 0x0, 0x0, 0x0},	/* CL = 6 - Not supported */
    		{0x0, 0x0, 0x0, 0x0},	/* CL = 7 - Not supported */
-			{0x9, 0x7, 0x9, 0x8},	/* CL = 8 */
-			{0x9, 0x7, 0xA, 0x7},	/* CL = 9 */
-			{0x9, 0x7, 0xB, 0x6},	/* CL = 10 */
+			{0x9, 0x7, 0x8, 0x9},	/* CL = 8 */
+			{0x9, 0x7, 0x7, 0xa},	/* CL = 9 */
+			{0x9, 0x7, 0x6, 0xb},	/* CL = 10 */
    	}
    };