Change in coreboot[master]: soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56053 )

Change subject: soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE
......................................................................

soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE

This change allows preloading the payload.

BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 23 ms.

Signed-off-by: Raul E Rangel 
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/fsp_s_params.c
M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
3 files changed, 13 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/56053/1

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 1bb9353..5712644 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -26,6 +26,7 @@
    select HAVE_CF9_RESET
    select HAVE_EM100_SUPPORT
    select HAVE_FSP_GOP
+	select HAVE_PAYLOAD_PRELOAD_CACHE
    select HAVE_SMI_HANDLER
    select IDT_IN_EVERY_STAGE
    select IOAPIC
diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index ae51f92..701beae 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-#include <fsp/api.h>
+#include <acpi/acpi.h>
 #include <device/pci.h>
+#include <fsp/api.h>
+#include <program_loading.h>

static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 {
@@ -13,4 +15,8 @@
    FSP_S_CONFIG *scfg = &supd->FspsConfig;

fsp_assign_vbios_upds(scfg);
+
+	/* Preload the payload while FSP-S runs */
+	if (!acpi_is_wakeup_s3())
+		payload_preload();
 }
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index e5044e6..a2133bc 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -97,6 +97,11 @@

EARLY_RESERVED_DRAM_END(.)

+#if CONFIG(HAVE_PAYLOAD_PRELOAD_CACHE)
+        . = ALIGN(64);
+        REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, 64)
+#endif
+
    RAMSTAGE(CONFIG_RAMBASE, 8M)
 }