[S] Change in coreboot[main]: soc/amd/common/psp_gen2: return status from soc_read_c2p38

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83447?usp=email )

Change subject: soc/amd/common/psp_gen2: return status from soc_read_c2p38
......................................................................

soc/amd/common/psp_gen2: return status from soc_read_c2p38

This sort-of reverts commit 00ec1b9fc7ba ("soc/amd/common/block/psp/
psp_gen2: simplify soc_read_c2p38") and is done as a preparation to
switch back to using the MMIO access to the PSP mailbox registers.

Change-Id: Icca3c7832295ae9932778f6a64c493e474dad507
---
M src/soc/amd/common/block/psp/psb.c
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
M src/soc/amd/common/block/psp/spl_fuse.c
4 files changed, 16 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83447/1

diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c
index be20fc8..a537bff 100644
--- a/src/soc/amd/common/block/psp/psb.c
+++ b/src/soc/amd/common/block/psp/psb.c
@@ -110,7 +110,11 @@
    	return CB_SUCCESS;
    }

-	status = soc_read_c2p38();
+	if (soc_read_c2p38(&status) != CB_SUCCESS) {
+		printk(BIOS_ERR, "PSP: Failed to get base address.\n");
+		return CB_ERR;
+	}
+
    printk(BIOS_INFO, "PSB: HSTI = %x\n", status);

const u32 psb_test_status = status & PSB_TEST_STATUS_MASK;
diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index f6efa21..104cabd 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -115,6 +115,6 @@
 /* This command needs to be implemented by the generation specific code. */
 int send_psp_command(u32 command, void *buffer);

-uint32_t soc_read_c2p38(void);
+enum cb_err soc_read_c2p38(uint32_t *msg_38_value);

#endif /* __AMD_PSP_DEF_H__ */
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index 98baf86..98136d1 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -169,7 +169,8 @@
    return 0;
 }

-uint32_t soc_read_c2p38(void)
+enum cb_err soc_read_c2p38(uint32_t *msg_38_value)
 {
-	return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
-}
+	*msg_38_value = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
+	return CB_SUCCESS;
+}
\ No newline at end of file
diff --git a/src/soc/amd/common/block/psp/spl_fuse.c b/src/soc/amd/common/block/psp/spl_fuse.c
index cb1fab0..b6e715a 100644
--- a/src/soc/amd/common/block/psp/spl_fuse.c
+++ b/src/soc/amd/common/block/psp/spl_fuse.c
@@ -8,12 +8,17 @@
 static void psp_set_spl_fuse(void *unused)
 {
    int cmd_status = 0;
+	uint32_t c2p38 = 0;
    struct mbox_cmd_late_spl_buffer buffer = {
    	.header = {
    		.size = sizeof(buffer)
    	}
    };
-	uint32_t c2p38 = soc_read_c2p38();
+
+	if (soc_read_c2p38(&c2p38) != CB_SUCCESS) {
+		printk(BIOS_ERR, "PSP: Failed to get base address.\n");
+		return;
+	}

if (c2p38 & CORE_2_PSP_MSG_38_FUSE_SPL) {
    	printk(BIOS_DEBUG, "PSP: SPL Fusing may be updated.\n");