Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning

[Bao Zheng (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held.
Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 )

Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
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Patch Set 3:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/59918/comment/fde7c122_2958ba36 
PS1, Line 8:
> Where is that documented?

Done

File src/soc/amd/cezanne/chip.h:

https://review.coreboot.org/c/coreboot/+/59918/comment/03999775_8267df11 
PS1, Line 111: 	/* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */
> Does this mean you will apply the same tuning parameters to multiple DPs?

Other DPs can be set in another request.