[XS] Change in coreboot[main]: soc/intel/common/block/pmc: Fix compilation error with MS4V=BIT(18)

[Subrata Banik (Code Review)]

Attention is currently required from: Saurabh Mishra.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email )

Change subject: soc/intel/common/block/pmc: Fix compilation error with MS4V=BIT(18)
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84142/comment/8f5a5bdd_39e1b653?usp... :
PS1, Line 9: If MS4V is defined using the BIT macro such in as in BIT(18) for
           : instance, it is replaced with (1ul << 18)
do you see this issue when selecting 64-bit Kconfig ?

if yes, then I believe the correct commit msg may be something similar

```
On a 64-bit system, 1ul will typically be 64 bits wide. The left shift can accommodate values of x up to 63 without overflowing. But `GEN_PMCON_A` register width is 32-bit hence, adding narrow typecasting to limit the register to max 32-bit width. 
```