Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46793 )
Change subject: broadwell: Flatten `acpi_init_gnvs` function ......................................................................
broadwell: Flatten `acpi_init_gnvs` function
Instead of relying on mainboards to call it, do like Lynx Point.
Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/pch/lpc.c 6 files changed, 26 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/46793/1
diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 54c23c9..5284cef 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/ioapic.h> #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <soc/acpi.h> @@ -9,8 +8,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1;
diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 4fe7815..1197c0c 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -2,7 +2,6 @@
#include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <arch/ioapic.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> @@ -10,8 +9,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1;
diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 8c894a8..21a94bc 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -2,7 +2,6 @@
#include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <arch/ioapic.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> @@ -10,8 +9,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1;
diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index a44808f..e127a56 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -2,11 +2,9 @@
#include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <arch/ioapic.h> #include <soc/acpi.h> #include <soc/nvs.h>
void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); } diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 651c5a4..7366642 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cbmem.h> #include <device/pci_ops.h> @@ -147,31 +148,6 @@ return cores; }
-void acpi_init_gnvs(struct global_nvs *gnvs) -{ - /* Set unknown wake source */ - gnvs->pm1i = -1; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 13ffd43..3102a5e 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -14,6 +14,8 @@ #include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <cbmem.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> #include <string.h> #include <soc/gpio.h> #include <soc/iobp.h> @@ -622,6 +624,29 @@
if (gnvs) { acpi_create_gnvs(gnvs); + + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + +#if CONFIG(CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + } + /* And tell SMI about it */ apm_control(APM_CNT_GNVS_UPDATE);
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46793 )
Change subject: broadwell: Flatten `acpi_init_gnvs` function ......................................................................
Patch Set 6: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46793 )
Change subject: broadwell: Flatten `acpi_init_gnvs` function ......................................................................
broadwell: Flatten `acpi_init_gnvs` function
Instead of relying on mainboards to call it, do like Lynx Point.
Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46793 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/pch/lpc.c 6 files changed, 25 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 970ec9d..5284cef 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -8,8 +8,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1;
diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 580c0b6..1197c0c 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -9,8 +9,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1;
diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 53c8926..21a94bc 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -9,8 +9,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1;
diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index df3d15e..e127a56 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -7,5 +7,4 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); } diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 3d5e74a..7366642 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -148,31 +148,6 @@ return cores; }
-void acpi_init_gnvs(struct global_nvs *gnvs) -{ - /* Set unknown wake source */ - gnvs->pm1i = -1; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 2111913..73b83e4 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -13,6 +13,8 @@ #include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <cbmem.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> #include <string.h> #include <soc/gpio.h> #include <soc/iobp.h> @@ -621,6 +623,29 @@
if (gnvs) { acpi_create_gnvs(gnvs); + + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + +#if CONFIG(CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + } + /* And tell SMI about it */ apm_control(APM_CNT_GNVS_UPDATE);
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)